Stacked FET with bottom epi size control and wraparound backside contact

Patent metadata

Field	Value
Publication number	US-12557627-B2
Application number	US-202318451952-A
Country	US
Kind code	B2
Filing date	Aug 18, 2023
Priority date	Aug 18, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

First claim

The invention claimed is:

1 . A semiconductor device, comprising:
a stacked transistor structure having field effect transistors on at least two levels, the at least two levels including a top side and bottom side; a bottom active region disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface, the leveled surface including two different semiconductor materials; and a backside contact in contact with the faceted backside surface forming a wraparound contact to reduce contact resistance.

2 . The semiconductor device as recited in claim 1 , wherein the leveled surface is contacted by a contact from the top side.

3 . The semiconductor device as recited in claim 1 , wherein the contact from the top side contacts the two different semiconductor materials.

4 . The semiconductor device as recited in claim 1 , wherein the backside contact passes through a shallow trench isolation (STI) region.

5 . The semiconductor device as recited in claim 4 , wherein the backside contact is disposed within a backside interlevel dielectric layer and the STI region includes a material that has an etch selectivity that is different than that of the backside interlevel dielectric layer.

6 . The semiconductor device as recited in claim 5 , wherein the backside interlevel dielectric layer includes a contact trench for the backside contact, the contact trench including corners below adjacent gate structures to maintain dielectric below the adjacent gate structures.

7 . The semiconductor device as recited in claim 1 , wherein bottom active regions include a same lateral dimension despite lateral size variations during formation.

8 . The semiconductor device as recited in claim 1 , wherein the leveled surface includes facets and the facets are filled with an amorphous semiconductor material.

9 . The semiconductor device as recited in claim 1 , wherein bottom active regions without the backside contact include a sacrificial placeholder connected to the faceted backside surface.

10 . A method for fabrication of a semiconductor device, comprising:
forming bottom active regions with a first semiconductor material through a shallow trench isolation region on a substrate, the bottom active regions including a faceted surfaces; filling regions between the bottom active regions with a second semiconductor material; recessing the second semiconductor material and the first semiconductor material to provide a level surface across the bottom active regions; laterally cutting the bottom active regions to provide a substantially uniform lateral dimension for each of the bottom active regions; forming a bottom interlevel dielectric layer (ILD); fabricating top structures including top active regions, gate structures and top metallization structures; removing the substrate from a bottom side; exposing the second semiconductor material on the bottom side of at least one of the bottom active regions; selectively removing the second semiconductor material to expose the faceted surfaces of the at least one of the bottom active regions; and forming a backside wraparound contact in contact with exposed surfaces including the faceted surfaces of the at least one of the bottom active regions.

11 . The method as recited in claim 10 , wherein forming the bottom active regions with a first semiconductor material through a shallow trench isolation (STI) region on a substrate includes:
forming a sacrificial placeholder through the STI region; and epitaxially growing the bottom active regions on the sacrificial placeholder.

12 . The method as recited in claim 11 , wherein exposing the second semiconductor material on the bottom side of at least one of the bottom active regions includes:
forming a backside interlevel dielectric layer of a material that is selectively etchable relative to material of the STI region; and opening up contact holes through the backside interlevel dielectric layer.

13 . The method as recited in claim 11 , wherein filling regions between the bottom active regions with the second semiconductor material includes:
selecting the second semiconductor material in accordance with a conductivity type of the bottom active regions of the sacrificial placeholder.

14 . The method as recited in claim 10 , wherein recessing the second semiconductor material and the first semiconductor material to provide the level surface across the bottom active regions includes evenly etching back the second semiconductor material and the first semiconductor material to provide a substantially uniform height for the bottom active regions.

15 . The method as recited in claim 10 , wherein laterally cutting the bottom active regions to provide the substantially uniform lateral dimension for each of the bottom active regions includes:
forming an organic planarizing layer (OPL) over the level surface; and etching through the OPL and portions of the bottom active regions to control the substantially uniform lateral dimension.

16 . The method as recited in claim 15 , wherein etching through the OPL and portions of the bottom active regions includes etching through portions of the second semiconductor material in contact with facets on a top side of the bottom active regions.

17 . A method for fabrication of a semiconductor device, comprising:
forming sacrificial placeholders through a shallow trench isolation (STI) region formed on a substrate; epitaxially growing bottom active regions with a first semiconductor material from the sacrificial placeholders, the bottom active regions including top faceted surfaces and bottom faceted surfaces; filling regions between the bottom active regions with a second semiconductor material; recessing the second semiconductor material and the first semiconductor material to provide a level surface across the bottom active regions; forming an organic planarizing layer (OPL) over the level surface; etching through the OPL and portions of the bottom active regions to cut a substantially uniform lateral dimension into the bottom active regions; forming a bottom interlevel dielectric layer (ILD); fabricating top structures including top active regions, gate structures and top metallization structures; applying a carrier wafer over the top structures; flipping the semiconductor device; removing the substrate from a bottom side; exposing the second semiconductor material on the bottom side of at least one of the bottom active regions including removing exposed sacrificial placeholders and opening up the STI region; selectively removing the second semiconductor material to expose the bottom faceted surfaces of the at least one of the bottom active regions; and forming a backside wraparound contact in contact with exposed surfaces including the bottom faceted surfaces of the at least one of the bottom active regions.

18 . The method as recited in claim 17 , wherein filling regions between the bottom active regions with the second semiconductor material includes:
selecting the second semiconductor material in accordance with a conductivity type of the bottom active regions.

19 . The method as recited in claim 17 , wherein recessing the second semiconductor material and the first semiconductor material to provide the level surface across the bottom active regions includes evenly etching back the second semiconductor material and the first semiconductor material to provide a substantially uniform height for the bottom ac

Assignees

• IBM

Inventors

• Xie Ruilong
• Strane Jay William
• Reboh Shay
• Anderson Brent A
• Wang Junli
• Chu Albert M

Classifications

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title