Stacked field-effect transistors

Patent metadata

Field	Value
Publication number	US-12183740-B2
Application number	US-202217805507-A
Country	US
Kind code	B2
Filing date	Jun 6, 2022
Priority date	Jun 6, 2022
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

Provided is a stacked field-effect transistor (FET). The stacked FET comprises a top device, a bottom device, and a transition region between the top device and the bottom device. The transition region includes a plurality of inner spacers and a first inter-layer dielectric (ILD). The ILD is formed between each of the plurality of inner spacers. The top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers. The second channel sheet thickness is larger than both the first channel sheet thickness and the first distance.

First claim

What is claimed is:

1. A stacked field-effect transistor (FET) comprising:
a top device;
a bottom device; and
a transition region between the top device and the bottom device, the transition region comprising a plurality of inner spacers separated by a first distance and a first inter-layer dielectric (ILD) formed between each of the plurality of inner spacers,
wherein the top and bottom devices have a first channel sheet thickness in a gate region and a second channel sheet thickness between inner spacers, the second channel sheet thickness being larger than both the first channel sheet thickness and the first distance.

2. The stacked FET of claim 1 , wherein the top and bottom devices are nanosheet transistors having the same doping type.

3. The stacked FET of claim 1 , wherein the top and bottom devices are nanosheet transistors having different doping types.

4. The stacked FET of claim 1 , wherein the top device comprises one or more top source/drain epitaxies and the bottom device comprises one or more bottom source/drain epitaxies.

5. The stacked FET of claim 4 , further comprising:
a second ILD formed on top of the top device;
a back-end-of-line (BEOL) formed on top of the second ILD;
a first contact connecting a first bottom source/drain epitaxy to the BEOL, wherein the first contact extends from the first bottom source/drain epitaxy through the first ILD, a first top source/drain epitaxy, and the second ILD.

6. The stacked FET of claim 5 , further comprising:
a second contact connecting a second top source/drain epitaxy to the BEOL, wherein the second contact extends from the second top source/drain epitaxy through the second ILD.

7. The stacked FET of claim 6 , further comprising:
a third ILD formed below the bottom device;
a backside interconnect formed below the third ILD; and
a third contact connecting a second bottom source/drain epitaxy to the backside interconnect, wherein the third contact extends from the second bottom source/drain epitaxy through the third ILD.

8. The stacked FET of claim 1 , wherein:
the second channel thickness is approximately 9 nm;
the first channel thickness is approximately 6 nm; and
the first distance is approximately 3 nm.

9. The stacked FET of claim 1 , wherein the top device is an nFET device and the bottom device is a pFET device.

10. A method of fabricating a stacked FET, the method comprising:
forming a nanosheet stack on top of a substrate, wherein the nanosheet stack comprises a plurality of semiconductor layers separated by sacrificial layers, wherein the nanosheet stack comprises a top region, a middle region, and a bottom region, the semiconductor layers in the top region having a first thickness, the semiconductor layers in the middle region having a second thickness, and the semiconductor layers in the bottom region having a third thickness, wherein the second thickness is smaller than both the first and third thicknesses;
patterning the nanosheet stack to form a plurality of nanosheet fins;
indenting the sacrificial layers in between the nanosheet fins;
forming inner spacers in the indents in the sacrificial layers;
forming one or more bottom source/drain epitaxies between the nanosheet fins in the bottom region;
indenting the semiconductor layers in the middle region;
forming a bottom inter-layer dielectric (ILD) on the one or more bottom source/drain epitaxies, wherein the bottom ILD fills in the indents in the semiconductor layers;
forming one or more top source/drain epitaxies on top of the bottom ILD;
forming a top ILD on the one or more top source/drain epitaxies;
removing the sacrificial layers;
trimming the semiconductor layers such that the semiconductor layers in the middle region are removed and the semiconductor layers in the top and bottom regions are thinned; and
forming a metal gate around the semiconductor layers.

11. The method of claim 10 , wherein forming the nanosheet stack comprises:
forming a bottom nanosheet stack, wherein the bottom nanosheet stack comprises a first plurality of semiconductor layers separated by a sacrificial material, the first plurality of semiconductor layers having the first thickness;
forming a middle nanosheet stack on top of the bottom nanosheet stack, wherein the middle nanosheet stack comprises a second plurality of semiconductor layers separated by a sacrificial material, the second plurality of semiconductor layers having the second thickness;
forming a top nanosheet stack on top of the middle nanosheet stack, wherein the top nanosheet stack comprises a third plurality of semiconductor layers separated by a sacrificial material, the third plurality of semiconductor layers having the third thickness.

12. The method of claim 10 , wherein forming the one or more bottom source/drain epitaxies comprises:
filling the region between the nanosheet fins with an organic planarization layer (OPL);
recessing the OPL such that a top of the OPL is between the top semiconductor layer in the middle region and the bottom semiconductor layer in the top region;
forming a protective spacer along sidewalls of the semiconductor layers and the inner spacers in the top region, wherein the protective spacer is deposited along the sidewalls selective to the OPL;
removing the OPL; and
growing the bottom source/drain epitaxy to replace the OPL.

13. The method of claim 12 , wherein forming the one or more bottom source/drain epitaxies further comprises:
recessing the bottom source/drain epitaxy such that the top of the bottom source/drain epitaxy is between the top semiconductor layer in the bottom region and the bottom semiconductor layer in the middle region.

14. The method of claim 13 , wherein forming the one or more top source/drain epitaxies on top of the bottom ILD comprises:
removing the protective spacer; and
growing the top source/drain epitaxy on top of the bottom ILD.

15. The method of claim 10 , further comprising:
forming a third ILD on top of the top ILD;
forming a first contact, the first contact extending from a first top source/drain epitaxy to a top of the third ILD;
forming a second contact, the first second extending from a first bottom source/drain epitaxy to the top of the third ILD; and
forming a back-end-of-line (BEOL) on top of the third ILD, the first contact, and the second contact.

16. The method of claim 15 , wherein forming the first contact comprises:
forming a first trench in the third ILD and the top ILD, the first trench extending from the top of the third ILD to the top source/drain epitaxy, thereby exposing a portion of the top source/drain epitaxy; and
filling the first trench with a conductive material.

17. The method of claim 15 , wherein forming the second contact comprises:
forming a second trench, the second trench extending from the bottom source/drain epitaxy through the bottom ILD, through a second top source/drain epitaxy, through the top ILD, and through the third ILD, thereby exposing a portion of the bottom source/drain epitaxy; and
filling the second trench with a conductive material.

18. A method comprising:
forming a top device comprising a first plurality of channel sheets separated by inner spacers and a metal gate;
forming a transition region comprising a plurality of inner spacers separated by a first distance and a first inter-layer dielectric (ILD) formed between each of the plurality of inner spacers; and
forming a bottom device comprising a second plurality of channel sheet separated by inner spacers and the metal gate,
wherein the top and

Assignees

• IBM

Inventors

• Xie Ruilong
• Cheng Kangguo
• Durfee Curtis S
• Strane Jay William
• Sung Min Gyu
• Frougier Julien
• Park Chanro

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title