Integrated circuit package with through void guard trace

Patent metadata

Field	Value
Publication number	US-11264338-B2
Application number	US-201815934191-A
Country	US
Kind code	B2
Filing date	Mar 23, 2018
Priority date	Mar 23, 2018
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit (IC) package, comprising:
a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace, the first portion of the void having a first widest width, and the second portion of the void having a second widest width greater than the first widest width, and wherein the guard trace has a width; and
a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace, and wherein the signal trace has a width less than the width of the guard trace.

2. The IC package of claim 1 , further comprising a dielectric material located between the guard trace and signal trace, wherein the dielectric material separates the signal trace from the guard trace.

3. The IC package of claim 1 , wherein the guard trace is at least twice as wide as the signal trace.

4. The IC package of claim 1 , wherein a width of the guard trace is at least ten percent greater than a width of the signal trace.

5. The IC package of claim 1 , wherein a width of the signal trace is between 40 and 60 micrometers, and wherein a width of the guard trace is between 80 and 120 micrometers.

6. The IC package of claim 5 , wherein a width of the void is greater than 200 micrometers.

7. The IC package of claim 1 , wherein the IC package further includes a ground plane of a type of conductive metal, and wherein the guard trace is of the type of conductive metal.

8. The IC package of claim 7 , wherein the void is encircled by the ground plane.

9. The IC package of claim 1 , wherein the void is an adhesion void.

10. The IC package of claim 1 , wherein the signal trace is to be utilized for transmission of a high-speed signal.

11. A computer device, comprising:
a circuit board; and
an integrated circuit (IC) package mounted to the circuit board, wherein the IC package includes:
a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace, the first portion of the void having a first widest width, and the second portion of the void having a second widest width greater than the first widest width, and wherein the guard trace has a width; and
a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace, and wherein the signal trace has a width less than the width of the guard trace.

12. The computer device of claim 11 , wherein the IC package further includes a dielectric material located between the guard trace and signal trace, and wherein the dielectric material isolates the signal trace from the guard trace.

13. The computer device of claim 11 , wherein the guard trace is at least twice as wide as the signal trace.

14. The computer device of claim 11 , wherein a width of the guard trace is at least ten percent greater than a width of the signal trace.

15. The computer device of claim 11 , wherein a width of the signal trace is between 40 and 60 micrometers, and wherein a width of the guard trace is between 80 and 120 micrometers.

16. The computer device of claim 15 , wherein a width of the void is greater than 200 micrometers.

17. The computer device of claim 11 , wherein the IC package further includes a ground plane of a type of conductive metal, and wherein the guard trace is of the type of conductive metal.

18. The computer device of claim 17 , wherein the void is encircled by the ground plane.

19. The computer device of claim 11 , wherein the void is an adhesion void.

20. The computer device of claim 11 , wherein the signal trace is to be utilized for transmission of a high-speed signal.

21. A substrate for an integrated circuit package, comprising:
a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace, the first portion of the void having a first widest width, and the second portion of the void having a second widest width greater than the first widest width, and wherein the guard trace has a width; and
a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace, and wherein the signal trace has a width less than the width of the guard trace.

22. The substrate of claim 21 , further comprising a dielectric material located between the guard trace and signal trace, wherein the dielectric material separates the signal trace from the guard trace.

23. The substrate of claim 21 , wherein the guard trace is at least twice as wide as the signal trace.

24. The substrate of claim 21 , wherein a width of the signal trace is between 40 and 60 micrometers, and wherein a width of the guard trace is between 80 and 120 micrometers.

25. The substrate of claim 21 , wherein the substrate further includes a ground plane of a type of conductive metal, and wherein the guard trace is of the type of conductive metal.

Assignees

• Intel Corp

Inventors

• Prabhakumar Ananth
• Srinivasan Krishna
• Sarkar Arnab

Classifications

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title