Via architecture for increased density interface

Patent metadata

Field	Value
Publication number	US-10475736-B2
Application number	US-201715718012-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Sep 28, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

First claim

What is claimed is:

1. A package substrate comprising:
a first metal layer and a second metal layer;
a ground plane in the first metal layer;
a first signal trace in the second metal layer, the first signal trace electrically coupled to
a first signal pad in the first metal layer by a first signal via;
a second signal trace in the second metal layer, the second signal trace electrically coupled to a second signal pad in the first metal layer by a second signal via;
a first ground trace in the second metal layer between the first signal trace and the second signal trace, the first ground trace electrically coupled to the ground plane by a first ground via; and
a second ground trace in the second metal layer, the second ground trace electrically coupled to the ground plane by a second ground via, and the second ground via having a width substantially similar to a width of the second ground trace;
wherein the first signal trace is between the first ground trace and the second ground trace.

2. The package substrate of claim 1 , wherein the first ground trace is electrically connected to the second ground trace by the ground plane.

3. The package substrate of claim 2 , wherein the ground plane comprises a patterned metal line electrically coupled to the first ground via and the second ground via.

4. The package substrate of claim 2 , wherein the ground plane comprises a ground plane on the first metal layer spanning an area of the first metal layer that covers the first signal trace.

5. The package substrate of claim 4 , wherein the package substrate comprises two adjacent signal traces in the second metal layer, the two adjacent signal traces defining a differential pair of signal traces; and
wherein the ground plane comprises a gap in a region of the first metal layer above the two adjacent signal traces defining the differential pair of signal traces.

6. The package substrate of claim 1 , wherein the ground plane is a first ground plane, the package substrate further comprises a third metal layer, the third metal layer comprises a second ground plane, the second metal layer between the first metal layer and the third metal layer, and the second ground plane is electrically connected to the ground trace by the first ground plane in the first metal layer.

7. The package substrate of claim 6 , wherein the second ground plane is electrically coupled to the first ground plane by a via traversing the second metal layer.

8. The package substrate of claim 1 , wherein the ground via comprises one of a self-aligned via or a zero-misaligned via.

9. The package substrate of claim 1 , wherein the first signal via and the second signal via comprise one of a self-aligned via or a zero-misaligned via.

10. The package substrate of claim 1 , wherein the package substrate comprises a plurality of signal traces in the second metal layer and a plurality of ground traces in the second metal layer, and wherein a number of signal traces is equal to a number of ground traces.

11. The package substrate of claim 1 , wherein the ground plane has a thickness between 10 μm and 15 μm.

12. The package substrate of claim 1 , wherein the ground plane has a thickness below 6 μm.

13. The package substrate of claim 1 , wherein the ground plane comprises copper.

14. The package substrate of claim 1 , further comprising:
a signal solder bump electrically coupled to the first signal pad;
a ground pad on the first metal layer, the ground pad electrically coupled to the ground plane; and
a ground solder bump electrically coupled to the ground pad.

15. The package substrate of claim 14 , wherein the first signal pad is a first level interconnect (FLI).

16. The package substrate of claim 15 , wherein the FLI comprises copper of a thickness between 1.4 μm and 1.6 μm.

17. The package substrate of claim 1 , wherein the first signal trace and the second signal trace are high speed input/output traces.

18. The package substrate of claim 1 , wherein the package substrate comprises a die edge, and wherein the ground plane comprises a surface metal on the first metal layer extending to the die edge.

19. A computing device comprising:
a processor mounted on a substrate;
wherein the substrate comprises:
a first metal layer and a second metal layer;
a ground plane in the first metal layer;
a first signal trace in the second metal layer, the first signal trace electrically coupled to a first signal pad in the first metal layer by a first signal via;
a second signal trace in the second metal layer, the second signal trace electrically coupled to a second signal pad in the first metal layer by a second signal via; and
a first ground trace in the second metal layer between the first signal trace and the second signal trace, the first ground trace electrically coupled to the ground plane by a first ground via;
a second ground trace in the second metal layer, the first signal trace between the first ground trace and the second ground trace, the second ground trace electrically coupled to the ground plane by a second ground via; and
a third ground trace in the second metal layer, the second signal trace between the first ground trace and the third ground trace, the third ground trace electrically coupled to the ground plane by a third ground via.

20. The package substrate of claim 1 , wherein the first signal via has a width substantially similar to a width of the first signal trace.

21. A package substrate comprising:
a first metal layer and a second metal layer;
a ground plane in the first metal layer;
a first signal trace in the second metal layer, the first signal trace electrically coupled to
a first signal pad in the first metal layer by a first signal via, and the first signal via having a width substantially equal to a width of the first signal trace;
a second signal trace in the second metal layer, the second signal trace electrically coupled to a second signal pad in the first metal layer by a second signal via, and the second signal via has a width substantially equal to a width of the second signal trace; and
a ground trace in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via.

22. The package substrate of claim 21 , wherein the ground plane is a first ground plane, the package substrate further comprises a third metal layer, the third metal layer comprises a second ground plane, the second metal layer between the first metal layer and the third metal layer, and the second ground plane is electrically connected to the ground trace by the first ground plane in the first metal layer.

23. The package substrate of claim 22 , wherein the second ground plane is electrically coupled to the first ground plane by a via traversing the second metal layer.

24. The package substrate of claim 21 , wherein the ground via has a width substantially equal to a width of the ground trace.

Assignees

• Intel Corp

Inventors

• Aleksov Aleksandar
• Sarkar Arnab
• Sain Arghya
• Darmawikarta Kristof
• Braunisch Henning
• Parmar Prashant D
• Sharan Sujit
• Swan Johanna M
• Eid Feras

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title