Guard ring design enabling in-line testing of silicon bridges for semiconductor packages

Patent metadata

Field	Value
Publication number	US-10418312-B2
Application number	US-201515749465-A
Country	US
Kind code	B2
Filing date	Oct 29, 2015
Priority date	Oct 29, 2015
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate having an insulating layer disposed thereon;
a metallization structure disposed on the insulating layer, the metallization structure comprising conductive routing disposed in a dielectric material stack, wherein an uppermost layer of the metallization structure comprises first and second pluralities of conductive pads thereon;
a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing, the first metal guard ring comprising a plurality of individual guard ring segments;
a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring, the second metal guard ring continuous around the first metal guard ring; and
electrical testing features disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring, the electrical testing features coupled to the conductive routing by metal lines passing through the first metal guard ring.

2. The semiconductor structure of claim 1 , wherein the electrical testing features comprises test pads for signal lines and for VSS lines.

3. The semiconductor structure of claim 1 , wherein the plurality of individual guard ring segments of the first metal guard ring is arranged in two adjacent lines of staggered individual guard ring segments.

4. The semiconductor structure of claim 1 , wherein the substrate has a perimeter, the semiconductor structure further comprising a metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

5. The semiconductor structure of claim 1 , wherein the second metal guard ring provides a hermetic seal for the metallization structure.

6. The semiconductor device of claim 1 , wherein at least one of the first metal guard ring or the second metal guard ring comprises a vertical stack of alternating metal lines and vias aligned along a common axis.

7. The semiconductor structure of claim 1 , wherein the conductive routing electrically couples the first plurality of conductive pads with the second plurality of conductive pads.

8. The semiconductor structure of claim 1 , wherein the substrate is free from having semiconductor devices disposed therein.

9. The semiconductor structure if claim 1 , wherein the substrate is a single crystalline silicon substrate.

10. A semiconductor structure, comprising:
a substrate having an insulating layer disposed thereon;
a metallization structure disposed on the insulating layer, the metallization structure comprising conductive routing disposed in a dielectric material stack, wherein an uppermost layer of the metallization structure comprises first and second pluralities of conductive pads thereon;
a first continuous metal guard ring disposed in the dielectric material stack and surrounding the conductive routing;
a second continuous metal guard ring disposed in the dielectric material stack and surrounding a first portion of the first continuous metal guard ring at a first distance from the first continuous metal guard ring, and surrounding a second portion of the first continuous metal guard ring at a second distance smaller than the first distance; and
electrical testing features disposed in the dielectric material stack, between the second portion of the first continuous metal guard ring and the metallization structure, the electrical testing features coupled to the conductive routing.

11. The semiconductor structure of claim 10 , wherein the electrical testing features comprises test pads for signal lines and for VSS lines.

12. The semiconductor structure of claim 10 , wherein the electrical testing features are disposed between the second portion of the first continuous metal guard ring and a plurality of individual guard ring segments arranged in two adjacent lines of staggered individual guard ring segments, and wherein the electrical testing features are coupled to the conductive routing by metal lines passing through the plurality of individual guard ring segments.

13. The semiconductor structure of claim 10 , wherein the substrate has a perimeter, the semiconductor structure further comprising a metal-free region of the dielectric material stack surrounding the second continuous metal guard ring, the metal-free region disposed adjacent to the second continuous metal guard ring and adjacent to the perimeter of the substrate.

14. The semiconductor structure of claim 10 , wherein one or both of the first continuous metal guard ring and the second continuous metal guard ring provides a hermetic seal for the metallization structure.

15. The semiconductor device of claim 10 , wherein at least one of the first metal guard ring or the second metal guard ring comprises a vertical stack of alternating metal lines and vias aligned along a common axis.

16. The semiconductor structure of claim 10 , wherein the conductive routing electrically couples the first plurality of conductive pads with the second plurality of conductive pads.

17. The semiconductor structure of claim 10 , wherein the substrate is free from having semiconductor devices disposed therein.

18. The semiconductor structure if claim 10 , wherein the substrate is a single crystalline silicon substrate.

19. A semiconductor package, comprising:
an embedded multi-die interconnection bridge (EMIB) comprising a silicon bridge disposed within a semiconductor package substrate, the silicon bridge comprising:
a silicon substrate having an insulating layer disposed thereon;
a metallization structure disposed on the insulating layer, the metallization structure comprising conductive routing disposed in a dielectric material stack;
an inner metal guard ring disposed in the dielectric material stack and surrounding the conductive routing;
an outer metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring; and
test pads for signal lines and for VSS lines, the test pads surrounded by at least the outer metal guard ring; and
first and second adjacent semiconductor dies disposed on the semiconductor package substrate and electrically coupled to one another by the conductive routing of the metallization structure of the silicon bridge.

20. The semiconductor package of claim 19 , wherein the first semiconductor die is a memory die, and the second semiconductor die is a logic die.

21. The semiconductor package of claim 19 , wherein the inner metal guard ring of the silicon bridge is a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing, the first metal guard ring comprising a plurality of individual guard ring segments, wherein the outer guard ring of the silicon bridge is a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring, and wherein the test pads of the silicon bridge are disposed between the first metal guard ring and the second metal guard ring, the test pads coupled to the conductive routing by metal lines passing through the first metal guard ring.

22. The semiconductor package of claim 19 , wherein the inner metal guard ring of the silicon bridge is a first continuous metal guard ring disposed in the dielectric material stack and surrounding the conductive routing, wherein the outer guard ring of the silicon bridge is

Assignees

• Intel Corp

Inventors

• Sarkar Arnab
• Sharan Sujit
• Kim Dae-Woo

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W90/00

  Package configurations · CPC title