Electroless metal-defined thin pad first level interconnects for lithographically defined vias

Patent metadata

Field	Value
Publication number	US-11728258-B2
Application number	US-202117536711-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Sep 29, 2017
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

First claim

We claim:

1. An integrated circuit (IC) package substrate, comprising:
a metal via extending to a top surface of a dielectric layer; and
a bond pad stack in contact with the metal via, the bond pad stack comprising a plurality of collocated layers, the collocated layers of the bond pad stack comprising:
a first layer comprising a reduced noble metal, a first portion of the reduced noble metal in contact with the metal via and a second portion of the reduced noble metal extending laterally from the metal via over the dielectric layer adjacent to the metal via, wherein a top of the metal via immediately adjacent the first portion of the reduced noble metal comprises oxidized metal; and
a second layer on the first layer, the second layer comprising a second metal.

2. The package substrate of claim 1 , wherein the reduced noble metal comprises reduced palladium)(Pd 0 ).

3. The package substrate of claim 1 , wherein the oxidized metal comprises oxidized copper (Cu 2+ ).

4. The package substrate of claim 1 , wherein the second metal comprises one of copper or nickel.

5. The package substrate of claim 4 , further comprising a third layer over the second layer, the third layer comprising a third metal wherein the third metal comprises at least one of cobalt, iron, tungsten, tin, gold, silver, palladium, platinum, ruthenium, rhodium, iridium, or osmium.

6. The package substrate of claim 1 , wherein the bond pad stack has a thickness less than 5 microns.

Assignees

• Intel Corp

Inventors

• Aleksov Aleksandar
• Strong Veronica
• Darmawikarta Kristof
• Sarkar Arnab

Classifications

• H10W70/095

  of vias therein · CPC title

• H10W70/66

  Conductive materials thereof · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/635 Primary

  Through-vias · CPC title

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title