Graphics processor register file including a low energy portion and a high capacity portion
US-12579072-B2 · Mar 17, 2026 · US
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Puffer David patents
Puffer David is listed as an inventor on 126 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Puffer David |
| Total patents | 126 |
| First publication | Jan 10, 2017 |
| Latest publication | Mar 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Flexible partitioning of GPU resources
US-12572392-B2 · Mar 10, 2026 · US
Multi-tile memory management
US-12554674-B2 · Feb 17, 2026 · US
Compression using a flat mapping in virtual address space
US-12518337-B2 · Jan 6, 2026 · US
Multi-render partitioning
US-12499503-B2 · Dec 16, 2025 · US
Local memory translation table accessed and dirty flags
US-12488410-B2 · Dec 2, 2025 · US
Engine to enable high speed context switching via on-die storage
US-2025348348-A1 · Nov 13, 2025 · US
Dynamically scalable and partitioned copy engine
US-12436705-B2 · Oct 7, 2025 · US
Engine to enable high speed context switching via on-die storage
US-12399734-B2 · Aug 26, 2025 · US
Scalable i/o virtualization interrupt and scheduling
US-2025209021-A1 · Jun 26, 2025 · US
Recent patents
Latest publications not already listed above.
Scalable centralized error queues in a processing architecture
US-2025209010-A1 · Jun 26, 2025 · US
Error injection architecture in a processing environment
US-2025209003-A1 · Jun 26, 2025 · US
Graphics processor data access and sharing
US-2025173308-A1 · May 29, 2025 · US
Multi-tile memory management
US-2025117356-A1 · Apr 10, 2025 · US
Page faulting and selective preemption
US-2025095099-A1 · Mar 20, 2025 · US
Accelerator controller hub
US-12229069-B2 · Feb 18, 2025 · US
Graphics processor data access and sharing
US-12204487-B2 · Jan 21, 2025 · US
Scalable I/O virtualization interrupt and scheduling
US-12197358-B2 · Jan 14, 2025 · US
Multi-tile memory management
US-2025004981-A1 · Jan 2, 2025 · US
Multi-tile memory management
US-12182062-B1 · Dec 31, 2024 · US
Page faulting and selective preemption
US-12131402-B2 · Oct 29, 2024 · US
Multi-tile memory management
US-12099461-B2 · Sep 24, 2024 · US
Page faulting and selective preemption
US-12067641-B2 · Aug 20, 2024 · US
Graphics processor data access and sharing
US-2024256483-A1 · Aug 1, 2024 · US
Sector cache for compression
US-2024232094-A1 · Jul 11, 2024 · US
Scalable i/o virtualization interrupt and scheduling
US-2024095201-A1 · Mar 21, 2024 · US
Assistance for hardware prefetch in cache access
US-11934342-B2 · Mar 19, 2024 · US
Sector cache for compression
US-11868264-B2 · Jan 9, 2024 · US
Engine to enable high speed context switching via on-die storage
US-2024004833-A1 · Jan 4, 2024 · US
Hybrid low power homogenous grapics processing units
US-2024004713-A1 · Jan 4, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 124 |
| Koker Altug | 3 |
| Puffer David | 3 |
| Ray Joydeep | 3 |
| Appu Abhishek R | 3 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 91 |
| G06T1/60 | 71 |
| G06F2212/302 | 32 |
| G06F12/0802 | 32 |
| G06F9/3888 | 31 |