Page faulting and selective preemption

Patent metadata

Field	Value
Publication number	US-12131402-B2
Application number	US-202217749275-A
Country	US
Kind code	B2
Filing date	May 20, 2022
Priority date	Apr 9, 2017
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

First claim

What is claimed is:

1. A graphics processor comprising:
a system interface; and
circuitry coupled with the system interface, the circuitry including an execution resource and a preemption status register, wherein the execution resource is configured to execute an instruction and during execution of the instruction, the execution resource is to:
receive a request to preempt execution of a thread associated with the instruction; and
based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread, wherein the preemption status register is to store a preemption hint including a multi-bit value that encodes an indication of an amount of register file space in use and a pending change in the amount of register file space in use.

2. The graphics processor as in claim 1 , wherein the circuitry includes a decode unit to:
decode the instruction and metadata associated with the instruction; and
set a value of the preemption status register based at least in part on the metadata.

3. The graphics processor as in claim 1 , wherein the preemption status register is configured to store a value that indicates whether preemption for the thread is enabled or disabled.

4. The graphics processor as in claim 3 , wherein the circuitry, in response to the request to preempt execution of the thread associated with the instruction, is to:
determine, based on the preemption status register, that preemption for the thread is disabled; and
execute the at least one additional instruction.

5. The graphics processor as in claim 3 , wherein the circuitry, in response to the request to preempt execution of the thread associated with the instruction, is to:
determine, based on the preemption status register, that preemption for the thread is enabled; and
preempt execution of the thread upon completion of execution of the at least one additional instruction.

6. The graphics processor as in claim 1 , wherein the execution resource has a single instruction multiple thread (SIMT) architecture.

7. The graphics processor as in claim 1 , wherein the preemption hint is to indicate that execution of the at least one additional instruction will cause a reduction of a size of a context save state.

8. A method comprising:
on a graphics processor having circuitry including an execution resource and a preemption status register:
executing an instruction via the execution resource;
receiving a request to preempt execution of a thread associated with an instruction; and
based on a value stored in the preemption status register, executing at least one additional instruction after receipt of the request to preempt execution of the thread, wherein the preemption status register is to store a preemption hint including a multi-bit value encoding an indication of an amount of register file space in use and a pending change in the amount of register file space in use.

9. The method as in claim 8 , further comprising:
decoding the instruction and metadata associated with the instruction; and
setting a value of the preemption status register based at least in part on the metadata.

10. The method as in claim 8 , wherein the value of the preemption status register indicates whether preemption for the thread is enabled or disabled.

11. The method as in claim 10 , further comprising:
in response to the request to preempt execution of the thread associated with the instruction:
determining, based on the preemption status register, that preemption for the thread is disabled; and
executing the at least one additional instruction.

12. The method as in claim 11 , wherein the circuitry, in response to the request to preempt execution of the thread associated with the instruction, is to:
determine, based on the preemption status register, that preemption for the thread is enabled; and
preempt execution of the thread upon completion of execution of the at least one additional instruction.

13. The method as in claim 8 , wherein the execution resource has a single instruction multiple thread (SIMT) architecture.

14. The method as in claim 13 , wherein the preemption hint is to indicate that execution of the at least one additional instruction will cause a reduction of a size of a context save state.

15. A data processing system comprising:
a memory device configured to store an instruction; and
a graphics processor coupled to the memory device, the graphics processor including:
circuitry including an execution resource and a preemption status register, wherein the execution resource is configured to execute the instruction and during execution of the instruction, the execution resource is to:
receive a request to preempt execution of a thread associated with the instruction; and
based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread, wherein the preemption status register is to store a preemption hint including a multi-bit value that encodes an indication of an amount of register file space in use and a pending change in the amount of register file space in use.

16. The data processing system as in claim 15 , wherein the circuitry includes a decode unit to:
decode the instruction and metadata associated with the instruction; and
set a value of the preemption status register based at least in part on the metadata.

17. The data processing system as in claim 15 , wherein the preemption status register is configured to store a value that indicates whether preemption for the thread is enabled or disabled.

18. The data processing system as in claim 17 , wherein the circuitry, in response to the request to preempt execution of the thread associated with the instruction, is to:
determine, based on the preemption status register, that preemption for the thread is disabled; and
execute the at least one additional instruction.

19. The data processing system as in claim 17 , wherein the circuitry, in response to the request to preempt execution of the thread associated with the instruction, is to:
determine, based on the preemption status register, that preemption for the thread is enabled; and
preempt execution of the thread upon completion of execution of the at least one additional instruction.

20. The data processing system as in claim 15 , wherein the preemption hint is to indicate that execution of the at least one additional instruction will cause a reduction of a size of a context save state.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Wald Ingo
• Puffer David
• Maiyuran Subramaniam M
• Surti Prasoonkumar
• Vembu Balaji
• Lueh Guei-Yuan
• Ramadoss Murali
• Appu Abhishek R
• Ray Joydeep

Classifications

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F9/461

  Saving or restoring of program or task context · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title