Multi-render partitioning

Patent metadata

Field	Value
Publication number	US-12499503-B2
Application number	US-202217827444-A
Country	US
Kind code	B2
Filing date	May 27, 2022
Priority date	Mar 18, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

First claim

What is claimed is:

1 . A graphics processor comprising:
a hardware scheduler; and a plurality of graphics processing clusters coupled with the hardware scheduler, wherein the plurality of graphics processing clusters respectively include a plurality of graphics multiprocessors coupled via an interconnect configured to exchange data within a graphics processing cluster between the plurality of graphics multiprocessors and the plurality of graphics processing clusters is configurable to be partitioned into a plurality of isolated render partitions, each isolated render partition having fault isolation and independent rendering capability, a graphics processing cluster is configurable into multiple render slices, and the plurality of isolated render partitions respectively include at least one render slice.

2 . The graphics processor as in claim 1 , wherein the hardware scheduler is configured to schedule a plurality of rendering workloads to the plurality of isolated render partitions for concurrent execution.

3 . The graphics processor as in claim 1 , wherein the at least one render slice includes a composition of fixed function and programmable circuitry from multiple hardware regions of the graphics processor.

4 . The graphics processor as in claim 1 , wherein a render slice of the multiple render slices includes a partition of a graphics processing cluster including a group of graphics multiprocessors of the graphics processing cluster.

5 . The graphics processor as in claim 4 , wherein the render slice includes a geometry pipeline, a raster pipeline, and an interface to an interconnect configurable to couple the geometry pipeline and the raster pipeline of a first render slice with the geometry pipeline and the raster pipeline of a second render slice.

6 . The graphics processor as in claim 5 , wherein at least one of the plurality of isolated render partitions includes the first render slice and the second render slice and geometry pipelines and raster pipelines of the first render slice and the second render slice are configurable to perform cooperative rendering via the interconnect.

7 . The graphics processor as in claim 6 , wherein the geometry pipeline of the first render slice is configurable to generate polygon attribute data that is accessible to the raster pipeline of the second render slice via the interconnect.

8 . The graphics processor as in claim 7 , wherein interconnect is a programmable packet switched interconnect configurable to route raster and position data between render slices within an isolated render partition and disable communication between the geometry pipelines within a first isolated render partition and the raster pipelines within a second isolated render partition.

9 . The graphics processor as in claim 1 , wherein a first isolated render partition is configurable to output to a first display and a second isolated render partition is configurable to output to a second display.

10 . The graphics processor as in claim 9 , wherein the first isolated render partition and the second isolated render partition have independent voltage and frequency scaling and the first isolated render partition is configurable to operate at a different voltage and frequency than the second isolated render partition.

11 . A data processing system comprising:
a memory device including instructions; and a graphics processor configured to execute the instructions, wherein the graphics processor comprises a plurality of graphics processing clusters that respectively include a plurality of graphics multiprocessors coupled via an interconnect configured to exchange of data within a graphics processing cluster between the plurality of graphics multiprocessors, the plurality of graphics processing clusters is configurable to be partitioned into a plurality of isolated render partitions, a graphics processing cluster is configurable into multiple render slices, the plurality of isolated render partitions respectively include at least one render slice, and each isolated render partition has fault isolation, independent rendering capability, and independent voltage and frequency scaling that enables a first isolated render partition to operate at a different voltage and frequency than a second isolated render partition.

12 . The data processing system as in claim 11 , the graphics processor further comprising a hardware scheduler that is configured to schedule a plurality of rendering workloads to the plurality of isolated render partitions for concurrent execution.

13 . The data processing system as in claim 11 , wherein the plurality of isolated render partitions each include one or more render slices, each of the one or more render slices includes a partition of a graphics processing cluster, and the partition of the graphics processing cluster includes a group of graphics multiprocessors.

14 . The data processing system as in claim 13 , wherein each of the one or more render slices includes a geometry pipeline, a raster pipeline, and an interface to an interconnect configurable to couple the geometry pipeline and the raster pipeline of a first render slice with the geometry pipeline and the raster pipeline of a second render slice, wherein geometry pipelines and raster pipelines of the first render slice and the second render slice are configurable to perform cooperative rendering via the interconnect and the geometry pipeline of the first render slice is configurable to generate polygon attribute data that is accessible to the raster pipeline of the second render slice via the interconnect.

15 . The data processing system as in claim 14 , wherein the interconnect is a programmable packet switched interconnect configurable to route raster and position data between render slices within an isolated render partition and disable communication between the geometry pipelines within a first isolated render partition and the raster pipelines within a second isolated render partition.

16 . A method comprising:
initializing partition management data used to enable a partitioned render engine of a partitionable graphics processor of a multi-client workstation device; configuring, via the partition management data, render slice and render front end assignments for partitions of the partitioned render engine, wherein a render slice includes a partition of a graphics processing cluster of the partitionable graphics processor, the partition of the graphics processing cluster including a group of graphics multiprocessors; configuring geometry distribution bus isolation and topology according to a render slice configuration for the partitions to enable communication isolation and facilitate fault isolation between partitions associated with different clients; configuring crossbar isolation and topology according to the render slice configuration for the partitions; performing multiple rendering operations in parallel via the partitions of the partitioned render engine.

17 . The method as in claim 16 , further comprising:
performing a first render operation for a first client of the multi-client workstation device via a first render partition; concurrently performing a second render operation for a second client of the multi-client workstation device via a second render partition; presenting output generated by the first render partition to a first display via a first display connector of the multi-client workstation; and presenting output generated by the second render partition to a second display via a second display connector of the multi-client workstat

Assignees

• Intel Corp

Inventors

• Nalluri Hema Chand
• Boles Jeffery S
• Cowperthwaite David
• Navale Aditya
• Surti Prasoonkumar
• Hunter Arthur
• Ranganathan Vasanth
• Ray Joydeep
• Puffer David
• Shah Ankur
• Krishnan Vidhya
• Bala Kritika
• Anantaraman Aravindh
• Apodaca Michael
• Daxer Kenneth

Classifications

• G06T2200/16

  involving adaptation to the client's capabilities · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T1/60

  Memory management · CPC title

• G06F9/5061

  Partitioning or combining of resources · CPC title

• G06F9/505

  considering the load · CPC title