Engine to enable high speed context switching via on-die storage

Patent metadata

Field	Value
Publication number	US-12399734-B2
Application number	US-202318349386-A
Country	US
Kind code	B2
Filing date	Jul 10, 2023
Priority date	Apr 1, 2017
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
processing circuitry coupled to a first memory, the processing circuitry having processing resources such that the first memory is shared by the processing resources, the processing circuitry to upload context data associated with the processing resources from the first memory to a second memory and restore the first memory, wherein the first memory is independent of and separate from the second memory and coupled to a high-bandwidth communication fabric, wherein the context data is uploaded from the first memory into a local memory,
wherein upon uploading the context data from the first memory into the local memory, a signal is generated to indicate that a context preemption process is complete,
wherein when the context preemption process is initiated, execution of an existing context on the one or more processing resources is terminated, and
wherein the processing circuitry is further to copy context state data from the existing context to the first memory in parallel with executing a context on one or more of the processing resources, wherein the first memory is restored.

2. The apparatus of claim 1 , wherein the processing circuitry comprises one or more of graphics processing circuitry or application processing circuitry.

3. A method comprising:
uploading, by a processor of a computing device, context data associated with processing resources of the processor from a first memory to a second memory and restore the first memory, wherein the first memory is independent of and separate from the second memory and coupled to a high-bandwidth communication fabric, wherein the context data is uploaded from the first memory into a local memory, wherein the first memory is shared by the processing resources,
wherein upon uploading the context data from the first memory into the local memory, a signal is generated to indicate that a context preemption process is complete,
wherein when the context preemption process is initiated, execution of an existing context on the one or more processing resources is terminated; and
copying context state data from the existing context to the first memory in parallel with executing a context on one or more of the processing resources, wherein the first memory is restored.

4. The method of claim 3 , wherein the processor comprises one or more of a graphics processor or an application processor.

5. At least one non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to facilitate operations comprising:
uploading context data associated with processing resources of a processor from a first memory to a second memory and restore the first memory, wherein the first memory is independent of and separate from the second memory and coupled to a high-bandwidth communication fabric, wherein the context data is uploaded from the first memory into a local memory, wherein the first memory is shared by the processing resources,
wherein upon uploading the context data from the first memory into the local memory, a signal is generated to indicate that a context preemption process is complete,
wherein when the context preemption process is initiated, execution of an existing context on the one or more processing resources is terminated; and
copying context state data from the existing context to the first memory in parallel with executing a context on one or more of the processing resources, wherein the first memory is restored.

6. The non-transitory computer-readable medium of claim 5 , wherein the computing device comprises the processor having one or more of a graphics processor or an application processor.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Surti Prasoonkumar
• Puffer David
• Maiyuran Subramaniam
• Lueh Guei-Yuan
• Appu Abhishek R
• Ray Joydeep
• Vembu Balaji
• Bar-On Tomer
• Lauritzen Andrew T
• Labbe Hugues
• Gierach John G
• Liktor Gabor

Classifications

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F12/1045

  associated with a data cache · CPC title

• G06F12/1036

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F16/172

  Caching, prefetching or hoarding of files · CPC title

• G06F16/113

  Details of archiving (lifecycle management in storage systems G06F3/0649; point-in-time backing up or restoration of persistent data G06F11/1446) · CPC title