Local memory translation table accessed and dirty flags

Patent metadata

Field	Value
Publication number	US-12488410-B2
Application number	US-202217849165-A
Country	US
Kind code	B2
Filing date	Jun 24, 2022
Priority date	Mar 18, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Embodiments described herein provide techniques to facilitate access to local memory of a graphics processor by a guest software domain. The guest software domain can access the local memory via an address translation system that includes a local memory translation table. In one embodiment, accessed and/or dirty bits are enabled in the local memory translation table, which may be used to accelerate the GPU local memory portion of VM Migration for a VM that includes a vGPU.

First claim

What is claimed is:

1 . A graphics processor comprising:
a system interface including a device interface configurable for assignment to a guest software domain; a local memory device; and processing circuitry including a plurality of graphics engines, the processing circuitry coupled with the local memory device, wherein the processing circuitry includes memory arbiter circuitry to arbitrate access to the local memory device, the memory arbiter circuitry configured, in response to a request from a graphics engine of the plurality of graphics engines to access memory via a virtual address, to:
perform a first address translation for the virtual address via a page table entry within a first translation table, the first address translation to generate a first physical address;
determine, via a local memory bit within the page table entry, whether the access is to the local memory device; and
perform a second address translation on the first physical address to generate a second physical address, the second address translation performed via an entry in a local memory translation table (LMTT) in response to a determination that the access is to the local memory device, the LMTT stored in the local memory device, wherein the entry of the LMTT includes a dirty bit to indicate that a modification has been made to a page associated with the second physical address.

2 . The graphics processor as in claim 1 , wherein the processing circuitry is configured to enable dirty page tracking for the LMTT in response to receipt of a command to enable dirty page tracking.

3 . The graphics processor as in claim 2 , wherein the processing circuitry, while dirty page tracking is enabled, is configured to:
process a request to perform a memory operation to a memory page of the local memory device; and in response to a determination that the memory operation is to cause a modification of data stored in the memory page, set the dirty bit in the LMTT entry associated with the memory page of the local memory device.

4 . The graphics processor as in claim 1 , wherein the LMTT entry includes an accessed bit to indicate that an access has occurred to the page associated with the second physical address.

5 . The graphics processor as in claim 4 , wherein the processing circuitry is configured to enable accessed page tracking in the LMTT in response to receipt of a command to enable accessed page tracking.

6 . The graphics processor as in claim 5 , wherein the processing circuitry, while accessed page tracking is enabled, is configured to:
process a request to perform a memory operation to a memory page of the local memory device; and set the accessed bit in the LMTT entry associated with the memory page of the local memory device.

7 . The graphics processor as in claim 1 , wherein the processing circuitry is configured to:
receive a request to perform a memory operation associated with a live migration of a guest software domain that is mapped to a virtual instance of the graphics processor; perform a page walk operation to gather a list of host physical addresses for dirty memory pages associated with the guest software domain; perform a batch copy of a first set of dirty local memory pages identified by the list into a back buffer of a double buffered dirty page buffer; flip the double buffered dirty page buffer such that the back buffer becomes a new front buffer and an existing front buffer becomes a new back buffer; and initiate an asynchronous transfer of dirty page data in the new front buffer to a destination associated with the live migration.

8 . The graphics processor as in claim 7 , wherein to perform the batch copy of the first set of dirty local memory pages includes to copy multiple dirty local memory pages in parallel.

9 . The graphics processor as in claim 7 , wherein the processing circuitry is configured to perform a batch copy of a second set of dirty local memory pages identified by the list into the new back buffer during the asynchronous transfer of the dirty page data in the new front buffer.

10 . The graphics processor as in claim 7 , wherein the processing circuitry is configured to:
clear the dirty bit for the entry in the LMTT after a copy of a memory page associated with the entry; set the dirty bit for the entry in the LMTT in association with a modification of memory page; and perform a second page walk operation to gather an updated list of host physical addresses for dirty memory pages associated with the guest software domain.

11 . A method comprising:
receiving a request to perform a memory operation associated with a live migration of a guest software domain that is mapped to a virtual instance of a graphics processor, the graphics processor configured to perform a first address translation for a virtual address via a first translation table associated with the graphics processor to generate a first physical address and a second address translation on the first physical address to generate a second physical address, the second address translation performed via an entry in a local memory translation table (LMTT), the LMTT stored in a local memory device of the graphics processor, wherein the entry of the LMTT includes a dirty bit to indicate that a modification has been made to a page associated with the second physical address; performing a page walk operation to gather a list of host physical addresses for dirty memory pages associated with the guest software domain; performing a batch copy of a first set of dirty local memory pages identified by the list into a back buffer of a double buffered dirty page buffer; flipping the double buffered dirty page buffer such that the back buffer becomes a new front buffer and an existing front buffer becomes a new back buffer; and initiating an asynchronous transfer of dirty page data in the new front buffer to a destination associated with the live migration.

12 . The method of claim 11 , comprising enabling dirty page tracking for the LMTT in response to receipt of a command to enable dirty page tracking.

13 . The method as in claim 12 , wherein performing dirty page tracking comprises:
processing a request to perform a memory operation to a memory page of the local memory device; and in response to determining that the memory operation causes a modification of data stored in the memory page, setting the dirty bit in the LMTT entry associated with the memory page of the local memory device.

14 . The method as in claim 11 , wherein the entry of the LMTT includes an accessed bit to indicate that an access has occurred to the page associated with the second physical address.

15 . The method as in claim 14 , comprising enabling accessed page tracking in the LMTT in response to receipt of a command to enable accessed page tracking, wherein access page tracking includes:
processing a request to perform a memory operation to a memory page of the local memory device; and setting the accessed bit in the LMTT entry associated with the memory page of the local memory device.

16 . A graphics processing system comprising:
a memory device; and a graphics processor coupled with the memory device, the graphics processor including:
a system interface including a device interface configurable for assignment to a guest software domain;
a local memory device; and
a processing circuitry including a plurality of graphics engines, the processing circuitry coupled with the local memory device, wherein the processing circuitry includes memory arbiter circuitry to arbitrate access to the local memory devic

Assignees

• Intel Corp

Inventors

• Puffer David
• Shah Ankur
• Cooray Niranjan
• Cowperthwaite David
• Navale Aditya

Classifications

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F2212/302

  In image processor or graphics adapter · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title