Scalable centralized error queues in a processing architecture

US2025209010A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025209010-A1
Application numberUS-202318394569-A
CountryUS
Kind codeA1
Filing dateDec 22, 2023
Priority dateDec 22, 2023
Publication dateJun 26, 2025
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

An apparatus to facilitate scalable centralized error queues in a processing architecture is disclosed. The apparatus includes a processor comprising a systems interface hosting an error aggregator, wherein the processor is to host at least one centralized error queue in the error aggregator, the at least one centralized error queue is to store error logs for errors detected by components of the processor; receive an error reporting message from a component of the components of the processor, the error reporting message corresponding to an error detected by the component; and log the error as an entry in the at least one centralized error queue based on an error type of the error.

First claim

Opening claim text (preview).

What is claimed is: 1 . An apparatus comprising: a processor comprising a systems interface hosting an error aggregator, wherein the processor is to: host at least one centralized error queue in the error aggregator, the at least one centralized error queue is to store error logs for errors detected by components of the processor; receive an error reporting message from a component of the components of the processor, the error reporting message corresponding to an error detected by the component; and log the error as an entry in the at least one centralized error queue based on an error type of the error. 2 . The apparatus of claim 1 , wherein the processor is further to identify, from the error reporting message, the error type of the error comprising one of a correctable error, an uncorrectable contained error, or an uncorrectable uncontained error, and wherein the at least one centralized error queue comprises one or more of a correctable centralized error queue, a centralized error queue, or an uncorrectable centralized error queue to store the errors of respective ones of the error type. 3 . The apparatus of claim 2 , wherein the error reporting message is in an uncorrectable error log format responsive to the error type comprising one of the uncorrectable contained error or the uncorrectable uncontained error. 4 . The apparatus of claim 2 , wherein the error reporting message is in a correctable error log format responsive to the error type comprising the correctable error. 5 . The apparatus of claim 1 , wherein the processor is further to update at least one of a centralized log read control register, a centralized log status register, or a centralized log control register to reflect an updated state of the at least one centralized error queue that logged the error. 6 . The apparatus of claim 5 , wherein a driver is to utilize the centralized log read control register, the centralized log status register, and the centralized log control register to read entries of the at least one centralized error queue and to clear the entries of the at least one centralized error queue. 7 . The apparatus of claim 1 , wherein the at least one centralized error queue maintains entries across a warm reset of the processor. 8 . The apparatus of claim 1 , wherein the at least one centralized error queue is written to utilizing a quad-word write having an upper 32 bits carrying an identifier (ID) of a unit performing the quad-word write, and a lower 32 bits carrying data of the quad-word write. 9 . The apparatus of claim 1 , wherein the processor comprises a graphics processing unit (GPU). 10 . A method comprising: hosting, by a processing device comprising a systems interface hosting an error aggregator, at least one centralized error queue in the error aggregator, the at least one centralized error queue to store error logs for errors detected by components of the processing device; receiving, by the processing device, an error reporting message from a component of the components of the processing device, the error reporting message corresponding to an error detected by the component; and logging, by the processing device, the error as an entry in the at least one centralized error queue based on an error type of the error. 11 . The method of claim 10 , further comprising identifying, from the error reporting message, the error type of the error comprising one of a correctable error, an uncorrectable contained error, or an uncorrectable uncontained error, and wherein the at least one centralized error queue comprises one or more of a correctable centralized error queue, an uncorrectable local centralized error queue, or an uncorrectable global centralized error queue is to store the errors of respective ones of the error type. 12 . The method of claim 11 , wherein the error reporting message is in an uncorrectable error log format responsive to the error type comprising one of the uncorrectable contained error or the uncorrectable uncontained error. 13 . The method of claim 11 , wherein the error reporting message is in a correctable error log format responsive to the error type comprising the correctable error. 14 . The method of claim 10 , further comprising updating at least one of a centralized log read control register, a centralized log status register, or a centralized log control register to reflect an updated state of the at least one centralized error queue that logged the error. 15 . The method of claim 14 , wherein a driver is to utilize the centralized log read control register, the centralized log status register, and the centralized log control register to read entries of the at least one centralized error queue and to clear the entries of the at least one centralized error queue. 16 . A non-transitory computer-readable medium having instructions stored thereon, which when executed by one or more processors, cause the one or more processors to: host, by a processing device of the one or more processors comprising a systems interface hosting an error aggregator, at least one centralized error queue in the error aggregator, the at least one centralized error queue is to store error logs for errors detected by components of the processing device; receive, by the processing device, an error reporting message from a component of the components of the processing device, the error reporting message corresponding to an error detected by the component; and log, by the processing device, the error as an entry in the at least one centralized error queue based on an error type of the error. 17 . The non-transitory computer-readable medium of claim 16 , wherein the one or more processors are further to identify, from the error reporting message, the error type of the error comprising one of a correctable error, an uncorrectable contained error, or an uncorrectable uncontained error, and wherein the at least one centralized error queue comprises one or more of a correctable centralized error queue, a centralized error queue, or an uncorrectable global centralized error queue is to store the errors of respective ones of the error type. 18 . The non-transitory computer-readable medium of claim 17 , wherein the error reporting message is in an uncorrectable error log format responsive to the error type comprising one of the uncorrectable uncontained error or the uncorrectable uncontained error; and wherein the error reporting message is in a correctable error log format responsive to the error type comprising the correctable error. 19 . The non-transitory computer-readable medium of claim 16 , wherein the one or more processors are further to update at least one of a centralized log read control register, a centralized log status register, or a centralized log control register to reflect an updated state of the at least one centralized error queue that logged the error. 20 . The non-transitory computer-readable medium of claim 19 , wherein a driver is to utilize the centralized log read control register, the centralized log status register, and the centralized log control register to read entries of the at least one centralized error queue and to clear the entries of the at least one centralized error queue.

Assignees

Inventors

Classifications

  • Processor architectures; Processor configuration, e.g. pipelining · CPC title

  • Storage of error reports, e.g. persistent data storage, storage using memory protection · CPC title

  • Error or fault reporting or storing · CPC title

  • Content or structure details of the error report, e.g. specific table structure, specific error fields · CPC title

  • Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

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What does patent US2025209010A1 cover?
An apparatus to facilitate scalable centralized error queues in a processing architecture is disclosed. The apparatus includes a processor comprising a systems interface hosting an error aggregator, wherein the processor is to host at least one centralized error queue in the error aggregator, the at least one centralized error queue is to store error logs for errors detected by components of th…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F11/0766. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jun 26 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).