Multi-tile memory management

Patent metadata

Field	Value
Publication number	US-12099461-B2
Application number	US-202017431034-A
Country	US
Kind code	B2
Filing date	Mar 14, 2020
Priority date	Mar 15, 2019
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a cache memory;
a high-bandwidth memory;
a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length; and
an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database.

2. The apparatus of claim 1 , wherein shader core is to decompress the first data element from a bit length less than bits to a bit length of 8 bits.

3. The apparatus of claim 1 , wherein the shader core is to decompress the first data element from a bit length between 9 bits and 15 bits to a bit length of 16 bits.

4. The apparatus of claim 1 , wherein the shader core is to decompress the first data element from a bit length between 17 bits and 31 bits to a bit length of 32 bits.

5. The apparatus of claim 1 , wherein the shader core is to decompress the first data element from a bit length between 33 bits and 63 bits to a bit length of 64 bits.

6. The apparatus of claim 1 , wherein the arithmetic logic unit (ALU) is to perform a vector compare operation at the second bit length.

7. The apparatus of claim 6 , wherein the arithmetic logic unit (ALU) is to write a result of the vector compare operation as a bit vector.

8. A method comprising:
decompressing, in processing element of a shader core communicatively coupled to a cache memory, a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length; and
forwarding the second data element to an arithmetic logic unit (ALU) for comparison to a target value provided in a query of the in-memory database.

9. The method of claim 8 , wherein shader core is to decompress the first data element from a bit length less than bits to a bit length of 8 bits.

10. The method of claim 8 , wherein the shader core is to decompress the first data element from a bit length between 9 bits and 15 bits to a bit length of 16 bits.

11. The method of claim 8 , wherein the shader core is to decompress the first data element from a bit length between 17 bits and 31 bits to a bit length of 32 bits.

12. The method of claim 8 , wherein the shader core is to decompress the first data element from a bit length between 33 bits and 63 bits to a bit length of 64 bits.

13. The method of claim 8 , wherein the arithmetic logic unit (ALU) is to perform a vector compare operation at the second bit length.

14. The method of claim 13 , wherein the arithmetic logic unit (ALU) is to write a result of the vector compare operation as a bit vector.

15. A non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
decompress, in processing element of a shader core communicatively coupled to a cache memory, a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length; and
forward the second data element to an arithmetic logic unit (ALU) for comparison to a target value provided in a query of the in-memory database.

16. The computer-readable medium of claim 15 , wherein shader core is to decompress the first data element from a bit length less than bits to a bit length of 8 bits.

17. The computer-readable medium of claim 15 , wherein the shader core is to decompress the first data element from a bit length between 9 bits and 15 bits to a bit length of 16 bits.

18. The computer-readable medium of claim 15 , wherein the shader core is to decompress the first data element from a bit length between 17 bits and 31 bits to a bit length of 32 bits.

19. The computer-readable medium of claim 15 , wherein the shader core is to decompress the first data element from a bit length between 33 bits and 63 bits to a bit length of 64 bits.

20. The computer-readable medium of claim 15 , wherein the arithmetic logic unit (ALU) is to perform a vector compare operation at the second bit length.

21. The computer-readable medium of claim 15 , wherein the arithmetic logic unit (ALU) is to write a result of the vector compare operation as a bit vector.

Assignees

• Intel Corp

Inventors

• Appu Abhishek R
• Koker Altug
• Anantaraman Aravindh
• Ould-Ahmed-Vall Elmoustapha
• Andrei Valentin
• Galoppo Von Borries Nicolas
• George Varghese
• Macpherson Mike
• Maiyuran Subramaniam
• Ray Joydeep
• Striramassarma Lakshminarayanan
• Janus Scott
• Insko Brent
• Ranganathan Vasanth
• Sinha Kamal
• Hunter Arthur
• Surti Prasoonkumar
• Puffer David
• Valerio James
• Shah Ankur N

Classifications

• G06F2212/652

  Page size control · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F2212/6026

  Prefetching based on access pattern detection, e.g. stride based prefetch · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title