Method and systems for energy efficiency and energy conservation including on-off keying for power control
US-10725524-B2 · Jul 28, 2020 · US
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Nasrullah Jawad patents
Nasrullah Jawad is listed as an inventor on 16 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Nasrullah Jawad |
| Total patents | 16 |
| First publication | Oct 1, 2015 |
| Latest publication | Jul 28, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Controlling processor consumption using on-off keying having a maxiumum off time
US-10168765-B2 · Jan 1, 2019 · US
Apparatus and method for flushing dirty cache lines based on cache activity levels
US-9965023-B2 · May 8, 2018 · US
Controlling power consumption of a processor using interrupt-mediated on-off keying
US-9766685-B2 · Sep 19, 2017 · US
Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states
US-9665144-B2 · May 30, 2017 · US
Apparatus and method for reduced core entry into a power state having a powered down core cache
US-2017003734-A1 · Jan 5, 2017 · US
First droop event mitigation by clock generation frequency staggering for core power delivery
US-2016370837-A1 · Dec 22, 2016 · US
Controlling processor consumption using on-off keying having a maximum off time
US-2016320832-A1 · Nov 3, 2016 · US
Apparatus and method for reduced core entry into a power state having a powered down core cache
US-9442849-B2 · Sep 13, 2016 · US
Method and systems for energy efficiency and energy conservation including on-off keying for power control
US-2016179175-A1 · Jun 23, 2016 · US
Recent patents
Latest publications not already listed above.
Controlling processor consumption using on-off keying having a maximum off time
US-9354694-B2 · May 31, 2016 · US
Method and apparatus for managing a spin transfer torque memory
US-9342403-B2 · May 17, 2016 · US
Block-level sleep logic
US-9329658-B2 · May 3, 2016 · US
Method and systems for energy efficiency and energy conservation including on-off keying for power control
US-9280190-B2 · Mar 8, 2016 · US
Semiconductor chip with adaptive BIST cache testing during runtime
US-9229872-B2 · Jan 5, 2016 · US
Method and apparatus for managing a spin transfer torque memory
US-2015278011-A1 · Oct 1, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 15 |
| Nasrullah Jawad | 3 |
| Kwan Kelvin | 3 |
| Samsung Electronics Co Ltd | 1 |
| Wilkerson Christopher | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| Y02D10/00 | 13 |
| G06F1/324 | 9 |
| G06F1/3296 | 9 |
| G06F1/3287 | 8 |
| G06F1/3275 | 4 |