Apparatus and method for flushing dirty cache lines based on cache activity levels

Patent metadata

Field	Value
Publication number	US-9965023-B2
Application number	US-201615264548-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	Dec 29, 2012
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.

First claim

What is claimed is:

1. A non-transitory machine readable medium having program code that when processed by a processor causes the processor to perform a method comprising:
determining at least one value corresponding to an activity level of a core of the processor and a rate at which dirty cache lines of a cache of the core are to be sent from said core to a storage external from said core, wherein the activity level includes a rate of stores and a rate of loads; and
sending the dirty cache lines from the cache to the storage external to the core in response to the at least one value.

2. The non-transitory machine readable medium of claim 1 , wherein said at least one value further corresponds to an activity level of a lower level cache.

3. The non-transitory machine readable medium of claim 2 , wherein said lower level cache is an L1 cache.

4. The non-transitory machine readable medium of claim 1 , wherein said at least one value further corresponds to an activity level of a higher level cache.

5. The non-transitory machine readable medium of claim 1 , wherein the storage external from the core is a second cache of the processor.

6. A non-transitory machine readable medium having program code that when executed by a machine causes the machine to perform a method comprising:
repeatedly reading a next cache line from a cache internal to a core of a processor at periodic time intervals to determine if the next cache line is a dirty cache line;
collecting a first activity level of the cache and a second activity level of a storage external to the core, wherein the collecting includes collecting a rate of cache stores, a rate of cache loads, and a rate of creation of dirty cache lines; and
sending the dirty cache line from the cache to the storage external to the core in response to the first activity level of the cache and the second activity level of the storage external to the core.

7. The non-transitory machine readable medium of claim 6 , wherein the method further comprises clearing information indicating that the dirty cache line is dirty after the sending.

8. The non-transitory machine readable medium of claim 6 , wherein the cache is an L2 cache and the processor includes an L1 cache within the core; and
the sending comprises sending the dirty cache line from the core to the storage external to the core in response to a third activity level of the L1 cache, the first activity level of the L2 cache, and the second activity level of the storage external to the core.

9. The non-transitory machine readable medium of claim 6 , wherein the method further comprises determining a total score from a combination of the first activity level and the second activity level, and the sending comprises sending the dirty cache line from the core to the storage external to the core in response to the total score not exceeding a threshold.

10. The non-transitory machine readable medium of claim 6 , wherein the sending comprises sending the dirty cache line from the core to the storage external to the core in response to a determination that the first activity level of the cache does not exceed a first activity threshold and the second activity level does not exceed a second activity threshold.

11. The non-transitory machine readable medium of claim 6 , wherein the method further comprises receiving a backpressure signal from circuitry having a path from the core to the storage, and the sending comprises sending the dirty cache line from the core to the storage external to the core in response to the first activity level of the cache, the second activity level of the storage external to the core, and the backpressure signal from the circuitry having the path from the core to the storage.

12. The non-transitory machine readable medium of claim 6 , wherein the method further comprises storing one or more values in register circuitry of the processor to control the periodic time intervals to determine if the next cache line is the dirty cache line.

13. The non-transitory machine readable medium of claim 6 , wherein the collecting includes collecting:
a rate of cache stores of a first level of the cache and a second level of the cache; and
a rate of cache loads of the first level of the cache and the second level of the cache.

14. The non-transitory machine readable medium of claim 6 , wherein the method further comprises repeatedly reading the next cache line and sending the dirty cache line to the storage before a decision is made to enter the core into a power state where the cache is powered down.

15. The non-transitory machine readable medium of claim 6 , wherein the method further comprises repeatedly reading the next cache line and sending the dirty cache line to the storage while the core is active.

16. A system comprising:
a processor comprising a core;
a cache powered with the core;
a storage powered external to the core; and
circuitry to repeatedly read a next cache line from the cache at periodic time intervals to determine if the next cache line is a dirty cache line and send the dirty cache line from the cache to the storage in response to a first activity level of the cache and a second activity level of the storage, wherein the first activity level and the second activity level include a rate of stores, a rate of loads, and a rate of creation of dirty cache lines.

17. The system of claim 16 , wherein the cache is an L2 cache.

18. The system of claim 17 , wherein the circuitry is coupled to an L1 cache of the core and is to send the dirty cache line from the core to the storage in response to a third activity level of the L1 cache, the first activity level of the L2 cache, and the second activity level of the storage.

19. The system of claim 16 , wherein the circuitry is to send the dirty cache line from the core to the storage in response to a total score, determined by the circuitry from a combination of the first activity level and the second activity level, not exceeding a threshold.

20. The system of claim 16 , wherein the circuitry is to send the dirty cache line from the core to the storage in response to a determination that the first activity level of the cache does not exceed a first activity threshold and that the second activity level does not exceed a second activity threshold.

21. The system of claim 16 , wherein the circuitry is to receive a backpressure signal for a path from the core to the storage and is to send the dirty cache line from the core to the storage along the path in response to the first activity level of the cache, the second activity level of the storage external to the core, and the backpressure signal.

22. The system of claim 16 , further comprising register circuitry to store one or more values to control the periodic time intervals to determine if the next cache line is the dirty cache line.

23. The system of claim 16 , wherein the first activity level and the second activity level includes:
a rate of stores of a first level of the cache and a second level of the cache; and
a rate of loads of the first level of the cache and the second level of the cache.

24. The system of claim 16 , wherein the circuitry is to repeatedly read the next cache line and send the dirty cache line to the storage before a decision is made to enter the core into a power state where the cache is powered down.

25. The system of claim 16 , wherein the circuitry is to repeatedly read the next cache line a

Assignees

• Intel Corp

Inventors

• Keppel David
• Kwan Kelvin
• Nasrullah Jawad

Classifications

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/121

  using replacement algorithms · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F12/122

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title