Controlling power consumption of a processor using interrupt-mediated on-off keying

Patent metadata

Field	Value
Publication number	US-9766685-B2
Application number	US-201313894642-A
Country	US
Kind code	B2
Filing date	May 15, 2013
Priority date	May 15, 2013
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of circuits to independently operate; and
a first logic coupled to the plurality of circuits to cause at least one of the plurality of circuits to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, each of the plurality of off times to be of a first off duration if no interrupt is pending during the off time and of a second off duration if an interrupt is pending during the off time, wherein the first off duration corresponds to a maximum off time for a platform including the processor and the second off duration corresponds to a maximum interrupt off time for a hardware device of the platform, wherein the first logic is to cause the at least one circuit to delay exit from a current on time when an interrupt is received.

2. The processor of claim 1 , wherein, after receipt of an interrupt, the first logic is to cause the at least one circuit to exit a current off time before the maximum interrupt off time if a time remaining for the current off time is greater than a minimum interrupt off time for the platform, the minimum interrupt off time corresponding to a threshold time before an end of the current off time.

3. The processor of claim 2 , wherein the first logic is to cause the at least one circuit to exit the current off time before the maximum interrupt off time based on credit information.

4. The processor of claim 3 , wherein the first logic is to accumulate the credit information when an on time has a duration less than a calculated on time.

5. The processor of claim 1 , further comprising a configuration storage to store the maximum off time, wherein the configuration register is to be updated responsive to reconfiguration of the platform to include a new hardware device.

6. The processor of claim 1 , wherein the first logic is to cause the at least one circuit to enter a first low power state when at least some of the plurality of off times exceed a threshold, and otherwise cause the at least one circuit to enter a second low power state, wherein the first low power state is deeper than the second low power state.

7. The processor of claim 1 , wherein the first logic is to cause the at least one circuit to have an on time having a first on duration when the on time follows an off time having the first off duration and to have an on time having a second on duration when the on time follows an off time having the second off duration, the first on duration longer than the second on duration.

8. The processor of claim 1 , wherein the first logic is to issue at least one power gate control signal to cause one or more switches to control an ON condition and an OFF condition for one or more of the plurality of circuits of the processor.

9. The processor of claim 1 , wherein the processor further comprises a power control unit (PCU) including the first logic, wherein the PCU is to select ON-OFF keying for a minimum voltage condition (Vmin) of the processor and to select a voltage-frequency scaling for a voltage condition of the processor greater than the Vmin.

10. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
exiting a low power state of at least one processing unit of a processor at a conclusion of a first maximum off time if no interrupt is received during the low power state, the first maximum off time corresponding to a maximum off time for a hardware device of the machine;
exiting the low power state at a conclusion of a second maximum off time if an interrupt is received during the low power state, the second maximum off time extending from receipt of the interrupt until the low power state is exited and is less than the first maximum off time, the second maximum off time corresponding to a maximum interrupt off time for a hardware device of the machine; and
entering an active state of the at least one processing unit from the low power state for an on time having a duration based at least in part on whether the low power state was of the first maximum off time or the second maximum off time.

11. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises exiting the low power state at a conclusion of a minimum off time if the interrupt is received prior to a threshold duration before the conclusion of the first maximum off time.

12. The non-transitory machine-readable medium of claim 11 , wherein the method further comprises exiting the low power state at the conclusion of the minimum off time based on credit information.

13. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises accumulating the credit information when an on time has a duration less than a calculated on time.

14. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises power controlling the one or more processing units, including issuing a power gate signal to one or more power gates of the processor, the power gates active to gate power during the low power state.

15. The non-transitory machine-readable medium of claim 10 , wherein the method further comprises power controlling the at least one processing unit according to ON-OFF keying for a minimum voltage condition (Vmin) of the processor and power controlling the one or more processing units according to a voltage-frequency scaling for a voltage condition of the processor greater than the Vmin.

16. A processor comprising:
an exit logic to cause at least one functional unit of the processor to be in a low power state for a first duration if no interrupt is received during the first duration and to cause the at least one functional unit to be in the low power state for a second duration if an interrupt is received during the second duration, the second duration less than the first duration, and wherein the first duration corresponds to a maximum off time for a platform including the processor and based on a responsiveness requirement of a component of the platform;
credit logic to update a credit value when an interrupt is received within a threshold duration of a conclusion of the first duration and the at least one functional unit is to remain in the low power state until the conclusion of the first duration, wherein, based at least in part on the credit value, the exit logic is to cause the at least one functional unit to be in the low power state for a third duration less than the second duration if an interrupt is received more than the threshold duration from the conclusion of the first duration; and
a cycle controller to issue at least one power control signal according to a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, wherein the plurality of on times and the plurality of off times are variable to substantially maintain a requested speed for the processor.

17. The processor of claim 16 , further comprising calculation logic to calculate an on duration for the at least one functional unit following the low power state based at least in part on whether the at least one functional unit was in the low power state for the first duration or the second duration.

18. The processor of claim 16 , wherein the processor comprises a multicore processor including a plurality of cores and a power control unit (PCU), the PCU including the exit logic and the cycle controller.

19. The proc

Assignees

• Intel Corp

Inventors

• Keppel David
• Nasrullah Jawad

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• Y02B60/1282

  Cross-Sectional Technologies · mapped topic

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02B60/32

  Cross-Sectional Technologies · mapped topic