Method and systems for energy efficiency and energy conservation including on-off keying for power control

Patent metadata

Field	Value
Publication number	US-10725524-B2
Application number	US-201615059186-A
Country	US
Kind code	B2
Filing date	Mar 2, 2016
Priority date	Dec 21, 2011
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
computing an ON period for power gates of the device and an OFF period for power gates of ON-OFF keying for the device during a minimum voltage (Vmin) condition; and
setting a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

2. The computer-implemented method of claim 1 , further comprising:
prior to computing the ON and OFF periods to be used for the ON-OFF keying, choosing the ON-OFF keying from a plurality of power control schemes including voltage frequency scaling and frequency only scaling.

3. The computer-implemented method of claim 1 , wherein the power gate control comprises one or more switches to control an ON condition and an OFF condition for one or more blocks of the device.

4. The computer-implemented method of claim 1 , further comprising:
initiating power control with power control software; and
computing the target frequency for the device based on one or more inputs.

5. The computer-implemented method of claim 1 , further comprising:
selecting a voltage frequency scaling for voltages greater than Vmin during non-Vmin conditions.

6. The computer-implemented method of claim 1 , further comprising:
prior to computing the ON and OFF periods to be used for the ON-OFF keying, monitoring one or more of workload and power using at least one monitor includes silicon age monitors.

7. A processor, comprising:
one or more processing elements to execute instructions of power control software to provide power control for energy efficiency and energy conservation; and
a power control block comprising,
one or more blocks under power control of the power control software to utilize on-off modulation based on voltage and frequency conditions, and an effective target frequency;
one or more power gates coupled to the one or more blocks, the one or more power gates to control an ON condition and an OFF condition for the one or more blocks of the device, wherein at least one processing element is to execute instructions of the power control software to control power consumption of the one or more blocks during a minimum voltage (Vmin) condition, to compute an ON period and an OFF period of the ON-OFF modulation for the one or more blocks, and, based on the ON-OFF modulation, to set a target operating condition including a target frequency and a target supply voltage and a power gate control for the one or more blocks.

8. The processor of claim 7 , wherein at least one processing element is further configured to execute instructions of the power control software to compute the target operating condition including a target frequency for the power control block based on one or more inputs.

9. The processor of claim 7 , wherein the power control block further comprises one or more voltage regulators to receive a voltage control input from the power control software and to provide controlled supply voltages for the one or more blocks.

10. The processor of claim 7 , wherein the at least one processing element is further configured to execute instructions of the power control software to compute an actual operating condition including an actual frequency and an actual supply voltage.

11. The processor of claim 7 , the power control block further comprises one or more clock generators to receive a frequency control input from the power control software and to provide one or more controlled frequencies of clock signals for the one or more blocks, wherein the ON-OFF modulation reduces power consumption of the one or more blocks by alternating between the ON condition and the OFF condition, wherein the one or more blocks while in the OFF condition eliminates or at least reduces leakage power.

Assignees

• Intel Corp

Inventors

• Nasrullah Jawad
• Kwan Kelvin
• Ditzel David Roger
• Svilan Vjekoslav

Classifications

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/324

  by lowering clock frequency · CPC title