Method and apparatus for managing a spin transfer torque memory

Patent metadata

Field	Value
Publication number	US-9342403-B2
Application number	US-201414228555-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Mar 28, 2014
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.

First claim

What is claimed is:

1. An apparatus comprising:
a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries and associated with a scrubbing interval; and
a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for a given entry, whether the scrubbing interval has elapsed and, if so, then to invalidate the given entry or re-fetch data for the given entry from a source and, if the scrubbing interval has not elapsed, then to perform error detection and/or correction on the given entry.

2. The apparatus as in claim 1 wherein the scrub engine further comprises:
scrub interval calculation logic to calculate a current scrubbing interval based on at least a current or anticipated temperature of the STT memory.

3. The apparatus as in claim 1 wherein the STT memory is implemented as a translation lookaside buffer (TLB) within the memory subsystem, and wherein the entries are TLB entries containing virtual-to-physical address translations.

4. The apparatus as in claim 1 wherein the STT memory comprises a Level 1 or Level 2 cache within the memory subsystem.

5. The apparatus as in claim 4 wherein the cache comprises an instruction cache.

6. The apparatus as in claim 1 further comprising:
a pointer to be incremented by the analysis and processing logic to point to a current entry to be processed.

7. The apparatus as in claim 1 wherein the analysis and processing logic will attempt to perform its operations on an entry opportunistically, by waiting for a clock cycle in which the STT memory is idle.

8. The apparatus as in claim 7 wherein performing operations opportunistically comprises searching for an opportunity to perform operations on the entry at a first point in time prior to the end of the scrubbing interval, wherein if the operations cannot be performed by the end of the scrubbing interval or a second point in time prior to the end of the scrubbing interval, then the operations are forced, potentially causing a conflict if the STT memory is not idle.

9. The apparatus as in claim 1 wherein the analysis and processing logic is to determine whether an operation needs to be performed on an entry based, at least in part, on how recently that entry has been read.

10. The apparatus as in claim 9 wherein if the entry has been read sufficiently recently, then the entry is skipped by the analysis and processing logic.

11. The apparatus as in claim 10 further comprising:
a clock for periodically sequencing through different possible values of one or more bits, wherein each entry, upon being read, is assigned a current value from the clock, and wherein the analysis and processing logic reads the clock at a later time to determine whether the entry has been read sufficiently recently.

12. The apparatus as in claim 1 wherein the scrubbing interval is set to include a temperature guard band so that memory scrub operations are performed more often than required for a current temperature.

13. The apparatus as in claim 12 wherein in response to detecting an increase in temperature, the analysis and processing logic performs one or more high priority scrub operations to perform error detection and/or correction on the entries within the guard band and performs invalidations and/or re-fetch of data outside of the guard band.

14. The apparatus as in claim 13 wherein the analysis and processing logic modifies the guard band based on the current temperature or anticipated changes in temperature.

15. The apparatus as in claim 1 wherein the scrubbing interval is set, at least in part, based on sleep states entered by the apparatus.

16. The apparatus as in claim 15 wherein setting the scrubbing interval based on sleep states comprises waking periodically to scrub the STT memory to retain data and/or switching from scrubbing the STT memory to a timeout.

17. A method implemented within a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries, the method comprising:
specifying a scrubbing interval based, at least in part, on an error rate of the STT memory;
determining, for a given entry of the STT memory, whether the specified scrubbing interval has elapsed;
if the specified scrubbing interval has elapsed, then invalidating the given entry or re-fetching data for the given entry from a source; and
if the scrubbing interval has not elapsed, then performing error detection and/or correction on the given entry.

18. The method as in claim 17 further comprising:
calculating a current scrubbing interval based, at least in part, on a current or anticipated temperature of the STT memory.

19. The method as in claim 17 wherein the STT memory is implemented as a translation lookaside buffer (TLB) within the memory subsystem, and wherein the entries are TLB entries containing virtual-to-physical address translations.

20. The method as in claim 17 wherein the STT memory comprises a Level-1 or Level-2 cache within the memory subsystem.

21. The method as in claim 20 wherein the cache comprises an instruction cache.

22. The method as in claim 17 further comprising incrementing a pointer to point to a current entry to be processed.

23. The method as in claim 17 further comprising:
attempting to perform operations on an entry opportunistically, by waiting for a clock cycle in which the STT memory is idle.

24. The method as in claim 23 wherein performing operations opportunistically comprises searching for an opportunity to perform operations on the entry at a first point in time prior to the end of the scrubbing interval, wherein if the operations cannot be performed by the end of the scrubbing interval or a second point in time prior to the end of the scrubbing interval, then the operations are forced, potentially causing a conflict if the STT memory is not idle.

25. The method as in claim 17 further comprising:
determining whether an operation needs to be performed on an entry based, at least in part, on how recently that entry has been read.

26. The method as in claim 25 wherein if the entry has been read sufficiently recently, then the entry is skipped.

27. The method as in claim 26 further comprising:
a clock for periodically sequencing through different possible values of one or more bits, wherein each entry, upon being read, is assigned a current value from the clock, and wherein the analysis and processing logic reads the clock at a later time to determine whether the entry has been read sufficiently recently.

28. The method as in claim 17 wherein the scrubbing interval is set to include a temperature guard band so that memory scrub operations are performed more often than required for a current temperature.

29. The method as in claim 28 wherein in response to detecting an increase in temperature, performing one or more high priority scrub operations to perform error detection and/or correction on the entries within the guard band and performs invalidations and/or re-fetch of data outside of the guard band.

30. The method as in claim 29 further comprising:
modifying the guard band based on the current temperature or anticipated changes in temperature.

31. The method as in claim

Assignees

• Intel Corp

Inventors

• Keppel David Pardo
• Naeimi Helia
• Nasrullah Jawad

Classifications

• G06F11/106 Primary

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G06F11/1016

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title