Process-based virtualization system for executing a secure application process
US-11461474-B2 · Oct 4, 2022 · US
This page is not indexed by search engines while we improve data quality.
Mackerras Paul patents
Mackerras Paul is listed as an inventor on 26 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Mackerras Paul |
| Total patents | 26 |
| First publication | Oct 22, 2015 |
| Latest publication | Oct 4, 2022 |
Notable patents
Publications ranked by popularity score, then publication date.
Process-based virtualization system for executing a secure application process
US-2021232693-A1 · Jul 29, 2021 · US
Secure memory implementation for secure execution of virtual machines
US-10831889-B2 · Nov 10, 2020 · US
Extending data range addressing
US-10761852-B2 · Sep 1, 2020 · US
Extending data range addressing
US-10761853-B2 · Sep 1, 2020 · US
Secure memory implementation for secure execution of virtual machines
US-2019392143-A1 · Dec 26, 2019 · US
Secure memory implementation for secure execution of Virtual Machines
US-10474816-B2 · Nov 12, 2019 · US
Hardware based isolation for secure execution of virtual machines
US-10387686-B2 · Aug 20, 2019 · US
Secure memory implementation for secure execution of virtual machines
US-10296741-B2 · May 21, 2019 · US
Secure memory implementation for secure execution of virtual machines
US-2019034628-A1 · Jan 31, 2019 · US
Recent patents
Latest publications not already listed above.
Hardware based isolation for secure execution of virtual machines
US-2019034666-A1 · Jan 31, 2019 · US
Secure memory implementation for secure execution of virtual machines
US-2019034627-A1 · Jan 31, 2019 · US
Selecting processor micro-threading mode
US-9766948-B2 · Sep 19, 2017 · US
Selecting processor micro-threading mode
US-9766946-B2 · Sep 19, 2017 · US
Selecting Processor Micro-Threading Mode
US-2017132049-A1 · May 11, 2017 · US
Selecting Processor Micro-Threading Mode
US-2017132050-A1 · May 11, 2017 · US
Extending data range addressing
US-2017090931-A1 · Mar 30, 2017 · US
Extending data range addressing
US-2017090932-A1 · Mar 30, 2017 · US
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
US-9330023-B2 · May 3, 2016 · US
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
US-9323692-B2 · Apr 26, 2016 · US
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
US-9317443-B2 · Apr 19, 2016 · US
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
US-9311249-B2 · Apr 12, 2016 · US
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
US-2015301950-A1 · Oct 22, 2015 · US
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
US-2015301953-A1 · Oct 22, 2015 · US
Managing translations across multiple contexts using a tlb with entries directed to multiple privilege levels and to multiple types of address spaces
US-2015301939-A1 · Oct 22, 2015 · US
Managing translations across multiple contexts using a tlb with entries directed to multiple privilege levels and to multiple types of address spaces
US-2015301951-A1 · Oct 22, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 26 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/45558 | 14 |
| G06F2009/45587 | 10 |
| G06F2212/1052 | 10 |
| G06F2212/50 | 8 |
| G06F9/5077 | 8 |