Selecting processor micro-threading mode

Patent metadata

Field	Value
Publication number	US-9766946-B2
Application number	US-201514938011-A
Country	US
Kind code	B2
Filing date	Nov 11, 2015
Priority date	Nov 11, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An approach is provided to dynamically select a micro-threading (MT) mode of each core of a processor based on a load on each of the respective cores while the processor is running a hypervisor. The approach sets a core's micro-threading mode to a whole-core mode (MT1) in response to identifying that the load on the selected core is at a light load level, sets the core's micro-threading mode to a two-way micro-threading mode (MT2) in response to identifying that the load on the selected core has increased above the light load level, and sets the selected core's micro-threading mode to a four-way micro-threading mode (MT4) in response to identifying that the load on the selected core is at a high load level.

First claim

What is claimed is:

1. An information handling system comprising:
one or more processors, wherein at least a selected one of the processors includes a plurality of cores that are able to execute in a plurality of micro-threading (MT) modes;
one or more data stores accessible by at least one of the processors;
a memory coupled to at least one of the processors; and
a set of computer program instructions stored in the memory and executed by at least one of the processors in order to select the micro-threading (MT) mode of each core of the selected processor based on a load on each of the respective cores while the selected processor is running a hypervisor, wherein the MT mode is selected by performing actions comprising:
dynamically setting a selected core's micro-threading mode to a whole-core mode (MT1) in response to identifying that the load on the selected core is at a first load level;
dynamically setting the selected core's micro-threading mode to a two-way micro-threading mode (MT2) in response to identifying that the load on the selected core has increased above the first load level to a second load level;
dynamically setting the selected core's micro-threading mode to a four-way micro-threading mode (MT4) in response to identifying that the load on the selected core has increased above the second load level to a third load level;
entering a quest context after the setting of the micro-threading mode; and
switching the micro-threading mode of the selected core to the whole-core mode (MT1) upon the selected core exiting from the guest context.

2. The information handling system of claim 1 wherein the actions further comprise:
selecting a primary virtual core to execute on the selected core;
scanning a plurality of preempted virtual cores; and
selecting one or more of the preempted virtual cores to execute as secondary virtual cores along with the primary virtual core.

3. The information handling system of claim 2 wherein the actions further comprise:
selecting the micro-threading mode based on the selection of the secondary virtual cores.

4. The information handling system of claim 3 wherein the actions further comprise:
in response to a task executing on the primary virtual core requiring a service from a host process:
placing the task on a preempted virtual cores list corresponding to a current CPU; and
selecting a different task to execute on the primary virtual core.

5. The information handling system of claim 4 wherein the actions further comprise:
performing the service by the host process on the task; and
removing the task from the preempted virtual cores list.

6. The information handling system of claim 3 wherein the actions further comprise:
performing any needed service in a host process in response to exiting from the guest context; and
for each virtual CPU (vCPU) task scheduled to execute on the selected virtual core:
add an entry to a vCore data structure pertaining to each vCPU task that is ready to execute on the selected virtual core;
selecting one of the vCPU tasks as the runner task for the selected virtual core, wherein the runner task executes on the primary virtual core; and
selecting one or more of the vCPU tasks as tasks to execute concurrently with the runner task on the selected virtual core.

7. A computer program product stored in a computer readable storage medium, comprising computer program code that, when executed by an information handling system, selects the micro-threading (MT) mode of each core of a processor based on a load on each of the respective cores while the selected processor is running a hypervisor, wherein the MT mode is selected by performing actions comprising:
dynamically setting a selected core's micro-threading mode to a whole-core mode (MT1) in response to identifying that the load on the selected core is at a first load level;
dynamically setting the selected core's micro-threading mode to a two-way micro-threading mode (MT2) in response to identifying that the load on the selected core has increased above the first load level to a second load level;
dynamically setting the selected core's micro-threading mode to a four-way micro-threading mode (MT4) in response to identifying that the load on the selected core has increased above the second load level to a third load level;
entering a quest context after the setting of the micro-threading mode; and
switching the micro-threading mode of the selected core to the whole-core mode (MT1) upon the selected core exiting from the guest context.

8. The computer program product of claim 7 wherein the actions further comprise:
selecting a primary virtual core to execute on the selected core;
scanning a plurality of preempted virtual cores; and
selecting one or more of the preempted virtual cores to execute as secondary virtual cores along with the primary virtual core.

9. The computer program product of claim 8 wherein the actions further comprise:
selecting the micro-threading mode based on the selection of the secondary virtual cores.

10. The computer program product of claim 9 wherein the actions further comprise:
in response to a task executing on the primary virtual core requiring a service from a host process:
placing the task on a preempted virtual cores list corresponding to a current CPU; and
selecting a different task to execute on the primary virtual core.

11. The computer program product of claim 10 wherein the actions further comprise:
performing the service by the host process on the task; and
removing the task from the preempted virtual cores list.

Assignees

• IBM

Inventors

• Mackerras Paul

Classifications

• G06F9/5077 Primary

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F9/223

  Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/5083 Primary

  Techniques for rebalancing the load in a distributed system · CPC title

• G06F2009/4557

  Distribution of virtual machine instances; Migration and load balancing · CPC title