Secure memory implementation for secure execution of virtual machines

Patent metadata

Field	Value
Publication number	US-10831889-B2
Application number	US-201916539537-A
Country	US
Kind code	B2
Filing date	Aug 13, 2019
Priority date	Jul 27, 2017
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A system, a method, and a computer program product for secure memory implementation for secure execution of virtual machines are provided. Data is processed in a first mode and a second mode, and commands are sent to a chip interconnect bus using real addresses, wherein the chip interconnect bus transports a number of bits for the real addresses. A memory controller is operatively coupled to a memory component. A secure memory range is specified by using range registers. If the real address is detected to be in the secure memory range to match a memory component address, a real address bit is set. If the real address is in the memory address hole, a security access violation is detected. If the real address is not in the secure address range and the real address bit is set, the security access violation is detected.

First claim

What is claimed is:

1. A computer implemented method comprising:
processing, by one or more computer processors, data in a first mode and a second mode, wherein a data processing unit sends commands to a chip interconnect bus using real addresses;
wherein the chip interconnect bus transports a number of bits for the real addresses;
wherein the chip interconnect bus is larger than a number of bits needed for a maximum memory range supported by the computer system;
wherein a first portion of the bits for real addresses which are not in the range of the supported maximum memory range is used to indicate whether to operate in the first mode or the second mode creating a memory address hole, and wherein a memory controller operatively coupled to a memory component;
specifying, by the one or more computer processors, a secure memory range by using range registers;
responsive to determining that the real address is detected to be in the secure memory range to match a memory component address, setting, by the one or more computer processors, a real address bit; and
responsive to determining that the real address is in the memory address hole, detecting, by the one or more computer processors, a security access violation.

2. The computer implemented method of claim 1 , wherein the chip interconnect bus operatively coupled to bus slaves which are parts of a secure memory or a normal memory, in accordance with the each of the bus slaves trusted or non-trusted functionality specified by the real address bit stored in a register.

3. The computer implemented method of claim 2 , further comprising:
responsive to determining that the real address bit is set to a first value, restricting, by the one or more computer processors, one of the bus slaves from accessing the secure memory and detect the security access violation.

4. The computer implemented method of claim 3 , further comprising:
writing into the normal memory, wherein a bus master is a component of a base address register and modified to send commands to the chip interconnect bus, and wherein the bus slaves respond to the commands;
responsive to an untrusted block initiating the commands, setting one of the bits for the real address to the first value; and
responsive to the untrusted block attempting to access secure components, reporting, by the one or more computer processors, an error.

5. The computer implemented method of claim 1 , wherein the computer system includes a configuration register to select the bits of the real addresses, based on the computer system memory configuration.

6. The computer implemented method of claim 5 , wherein the computer system memory configuration is selected from a plurality memory configurations, and wherein one of the plurality of memory configurations does not include a secure memory.

7. The computer implemented method of claim 1 , wherein the first mode is a normal operation mode and the second mode is a secure operation mode.

8. The computer implemented method of claim 1 , wherein the memory component includes dual in-line memory modules (DIMMs), and wherein the memory component includes at least one of: a direct attached memory component and a memory buffer chip.

9. A non-transitory computer program product comprising:
a data processing circuit to process data in a first mode and a second mode, and to send commands to a chip interconnect bus using real addresses;
wherein the chip interconnect bus transports a number of bits for the real addresses;
wherein the chip interconnect bus is larger than a number of bits needed for a maximum memory range supported by the computer system;
wherein a first portion of the bits for real addresses which are not in the range of the supported maximum memory range is used to indicate whether to operate in the first mode or the second mode creating a memory address hole;

a memory controller operatively coupled to a memory component;
one or more computer readable storage media;
program instructions stored on the one or more computer readable storage media for execution by one or more computer processors, the program instructions comprising:
program instructions to specify a secure memory range by using range registers;
program instructions to, responsive to determining that the real address is detected to be in the secure memory range to match a memory component address, set a real address bit;
program instructions to, responsive to determining that the real address is in the memory address hole, detect a security access violation; and
program instructions to, responsive to determining that the real address is not in the secure address range and the real address bit is set, detect the security access violation.

10. The non-transitory computer program product of claim 9 , wherein the chip interconnect bus operatively coupled to bus slaves which are parts of a secure memory or a normal memory, in accordance with the each of the bus slaves trusted or non-trusted functionality specified by the real address bit stored in a register.

11. The non-transitory computer program product of claim 10 , wherein the program instructions stored on the one or more computer readable storage media further comprise:
program instructions to, responsive to determining that the real address bit is set to a first value, restrict one of the bus slaves from accessing the secure memory and detect the security access violation.

12. The non-transitory computer program product of claim 11 , wherein the program instructions stored on the one or more computer readable storage media further comprise:
a bus master operated, by the processor, to write into the normal memory, wherein the bus master is a component of a base address register and modified to send commands to the chip interconnect bus, and wherein the bus slaves respond to the commands;
responsive to an untrusted block initiating the commands, the bus master operated, by the processor, to set one of the bits for the real address to the first value; and
responsive to the untrusted block attempting to access secure components, reporting an error.

13. The non-transitory computer program product of claim 9 , wherein the computer system includes a configuration register to select the bits of the real addresses, based on the computer system memory configuration.

14. The non-transitory computer program product of claim 13 , wherein the computer system memory configuration is selected from a plurality memory configurations, and wherein one of the plurality of memory configurations does not include a secure memory.

15. The non-transitory computer program product of claim 9 , wherein the first mode is a normal operation mode and the second mode is a secure operation mode.

16. The non-transitory computer program product of claim 9 , wherein the memory component includes dual in-line memory modules (DIMMs), and wherein the memory component includes at least one of: a direct attached memory component and a memory buffer chip.

17. A computer system for secure execution of virtual machines, the computer system comprising:
one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage medium, and program instructions stored on at least one of the one or more tangible storage medium for execution by at least one of the one or more processors via at least one of the one or more memories, wherein the computer system is capable of performing a method comprising:
processing, by one or more computer processors, data in a first mode and a second mode, wherein a data processing

Assignees

• IBM

Inventors

• Hall William E
• Hunt Guerney D H
• Kalla Ronald N
• Leenstra Jentje
• Mackerras Paul
• Starke William J
• Stuecheli Jeffrey A

Classifications

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F12/1441

  for a range · CPC title

• G06F13/404

  with address mapping · CPC title

• G06F21/53

  by executing in a restricted environment, e.g. sandbox or secure virtual machine · CPC title