Extending data range addressing

Patent metadata

Field	Value
Publication number	US-10761853-B2
Application number	US-201615194666-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Sep 30, 2015
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

Addressability of instructions and the addressing of data ranges are extended. One or more operands obtained from fields explicitly specified by an instruction are overridden (i.e., ignored), and instead, an address based on the instruction (e.g., an instruction address) is substituted for the one or more operands. This provides an address having more bits than allowed by the operand being overridden, thereby extending addressability of the instruction and extended data range addressing. Further, in one aspect, additional bits may be added to one or more immediate fields of the instruction, thereby extending addressability of the instructions and extending data range addressing.

First claim

What is claimed is:

1. A computer-implemented method of facilitating processing in a computing environment, the computer-implemented method comprising:
obtaining, by a processor, an instruction to be executed, the instruction explicitly specifying one or more fields to be used to obtain an operand to be employed by the instruction;
determining whether the instruction has a corresponding prefix instruction, the prefix instruction being another instruction from the instruction to be executed obtained by the processor;
based on determining that the instruction does not have the corresponding prefix instruction, obtaining, from a current instruction address of the instruction, an indication that the operand is to be ignored, the indication being one indicator of multiple indicators to be used in overriding the operand, the current instruction address including a selected address to be used to override the operand;
based on determining that the instruction has the corresponding prefix instruction, initiating a decoding of the instruction, the initiating determining whether the decoding of the instruction supports prefixing;
based on determining that the decoding of the instruction supports prefixing, determining whether a prefix of the prefix instruction includes the indication that the operand is to be ignored, the indication being one indicator of the multiple indicators to be used in overriding the operand and the prefix indicating the selected address to be used to override the operand;
based on obtaining the indication that the operand is to be ignored, replacing the operand with the selected address based on the instruction;
determining, via a specifier, whether an additional value is to be employed with the selected address, the specifier being another indicator of the multiple indicators;
modifying the selected address using the additional value, based on the specifier indicating the additional value is to be employed with the selected address; and
using the selected address to provide an extended address used by the instruction in addressing a table with an extended directly addressable data range, the extended address increasing a range of addressing by the instruction into the table.

2. The computer-implemented method of claim 1 , wherein the additional value includes one or more additional bits to extend the selected address, providing the extended address.

3. The computer-implemented method of claim 2 , wherein the prefix instruction further specifies the one or more additional bits.

4. The computer-implemented method of claim 3 , wherein the prefix instruction comprises one or more fields to specify the one or more additional bits.

5. The computer-implemented method of claim 3 , wherein the method further comprises:
decoding the prefix instruction, the decoding comprising placing the indication and the one or more additional bits in a register; and
using the register during the decoding of the instruction, where the decoding of the instruction includes the replacing of the operand with the selected address.

6. The computer-implemented method of claim 2 , wherein the prefix instruction further comprises the specifier to indicate whether the one or more additional bits are to be employed.

7. The computer-implemented method of claim 1 , wherein a size of the prefix instruction is a same size as a size of the instruction.

8. The computer-implemented method of claim 1 , wherein the instruction is a successor instruction and the prefix instruction includes an indicator indicating whether an address based on the successor instruction is to be used as a base address for the successor instruction.

9. The computer-implemented method of claim 8 , wherein the prefix instruction further includes a field including a value to be used to override selected bits of at least one operand of the successor instruction.

10. The computer-implemented method of claim 1 , wherein, based on the determining the decoding does not support prefixing, generating an error to be presented.

Assignees

• IBM

Inventors

• Frazier Giles R
• Gschwind Michael K
• Mackerras Paul

Classifications

• G06F9/3557

  using program counter as base address · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/30167

  of immediate specifier, e.g. constants · CPC title

• G06F9/30098

  Register arrangements · CPC title