Controlling instruction issue rate using credit-based mechanisms in processor devices
US-2026056597-A1 · Feb 26, 2026 · US
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Kanapathipillai Pradeep patents
Kanapathipillai Pradeep is listed as an inventor on 44 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kanapathipillai Pradeep |
| Total patents | 44 |
| First publication | May 26, 2015 |
| Latest publication | Feb 26, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Processors including power control circuits to reduce a no-load voltage to save power and increase longevity and related methods
US-12468377-B2 · Nov 11, 2025 · US
Converting telemetry values into common data formats in a processor-based system in an integrated circuit (IC) chip
US-12411748-B2 · Sep 9, 2025 · US
DSB Operation with Excluded Region
US-2025278274-A1 · Sep 4, 2025 · US
Performing thermal management based on temperature evolution models in processor devices
US-2025224787-A1 · Jul 10, 2025 · US
DSB operation with excluded region
US-12321746-B2 · Jun 3, 2025 · US
Processors including power control circuits to reduce a no-load voltage to save power and increase longevity and related methods
US-2025093942-A1 · Mar 20, 2025 · US
Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector Operations
US-2025094381-A1 · Mar 20, 2025 · US
Converting telemetry values into common data formats in a processor-based system in an integrated circuit (ic) chip
US-2024427682-A1 · Dec 26, 2024 · US
Coprocessors with bypass optimization, variable grid architecture, and fused vector operations
US-12174785-B2 · Dec 24, 2024 · US
Recent patents
Latest publications not already listed above.
Latency management in synchronization events
US-11914524-B2 · Feb 27, 2024 · US
Dynamic voltage and frequency scaling (DVFS) within processor clusters
US-11797045-B2 · Oct 24, 2023 · US
DSB Operation with Excluded Region
US-2023333851-A1 · Oct 19, 2023 · US
DSB operation with excluded region
US-11720360-B2 · Aug 8, 2023 · US
Hardware compression and decompression engine
US-11500638-B1 · Nov 15, 2022 · US
Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector Operations
US-2022358082-A1 · Nov 10, 2022 · US
DSB Operation with Excluded Region
US-2022083338-A1 · Mar 17, 2022 · US
Unified address translation
US-11221962-B2 · Jan 11, 2022 · US
Architected state retention for a frequent operating state switching processor
US-10990159-B2 · Apr 27, 2021 · US
Unified address translation
US-2021064539-A1 · Mar 4, 2021 · US
Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector Operations
US-2020272597-A1 · Aug 27, 2020 · US
Translation lookaside buffer invalidation by range
US-10725928-B1 · Jul 28, 2020 · US
Translation Lookaside Buffer Invalidation By Range
US-2020218663-A1 · Jul 9, 2020 · US
Unified prefetch circuit for multi-level caches
US-10621100-B1 · Apr 14, 2020 · US
Load/store dependency predictor optimization for replayed loads
US-10437595-B1 · Oct 8, 2019 · US
Out of order store commit
US-10228951-B1 · Mar 12, 2019 · US
Unified prefetch circuit for multi-level caches
US-10180905-B1 · Jan 15, 2019 · US
Load-store unit with banked queue
US-10133571-B1 · Nov 20, 2018 · US
Architected state retention
US-2018307297-A1 · Oct 25, 2018 · US
Execution unit power management
US-10037073-B1 · Jul 31, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Apple Inc | 36 |
| Qualcomm Inc | 8 |
| Kannan Hari S | 2 |
| Kanapathipillai Pradeep | 2 |
| Lilly Brian P | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3834 | 14 |
| Y02D10/00 | 13 |
| G06F9/30043 | 12 |
| G06F1/3206 | 9 |
| G06F1/3296 | 7 |