Out of order store commit

Patent metadata

Field	Value
Publication number	US-10228951-B1
Application number	US-201514831661-A
Country	US
Kind code	B1
Filing date	Aug 20, 2015
Priority date	Aug 20, 2015
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

Systems, apparatuses, and methods for committing store instructions out of order from a store queue are described. A processor may store a first store instruction and a second store instruction in the store queue, wherein the first store instruction is older than the second store instruction. In response to determining the second store instruction is ready to commit to the memory hierarchy, the processor may allow the second store instruction to commit before the first store instruction, in response to determining that all store instructions in the store queue older than the second store instruction are non-speculative. However, if it is determined that at least one store instruction in the store queue older than the second store instruction is speculative, the processor may prevent the second store instruction from committing to the memory hierarchy before the first store instruction.

First claim

What is claimed is:

1. A processor comprising:
a cache configured to store data retrieved from a memory;
a store queue comprising a plurality of entries, wherein each entry stores:
an identification of a store instruction;
an indication as to whether the store instruction is speculative or non-speculative; and
a pending miss request indicator which indicates, in response to a cache hit, that data targeted by the store instruction is available in a cache;

wherein the processor is configured to:
store a first store instruction in a first entry of the store queue; and
store a second store instruction in a second entry of the store queue, wherein the first store instruction is older than the second store instruction; and
in response to determining the second store instruction is ready to commit to a memory hierarchy:
allow the second store instruction to commit before the first store instruction, in response to determining:
an indication in the second entry indicates the second store instruction is non-speculative; and
a pending miss indicator in the second entry indicates data targeted by the second instruction is available in the cache; and

prevent the second store instruction from committing to the memory hierarchy before the first store instruction, in response to determining that at least one store instruction in the store queue older than the second store instruction is speculative.

2. The processor as recited in claim 1 , wherein store instructions in the store queue that are speculative are subject to being flushed, and store instructions in the store queue that are non-speculative are not subject to being flushed.

3. The processor as recited in claim 1 , wherein an indication in an entry of the store queue indicates a corresponding store instruction is non-speculative in response to a determination that all older stores to a same address as the store instruction are complete, all older loads are complete, all older barrier instructions are complete, and all older branch instructions are resolved.

4. The processor as recited in claim 1 , wherein the processor is configured to:
move the first and second store instructions from the store queue to a write buffer when the first and second store instructions become non-speculative;
commit the second store instruction to a cache from the write buffer responsive to determining the second store instruction is a cache hit; and
delay committing the first store instruction to the cache from the write buffer responsive to determining the first store instruction is a cache miss.

5. The processor as recited in claim 4 , wherein the processor is configured to prevent a non-speculative store instruction from moving from the store queue to the write buffer responsive to determining both a youngest entry and an oldest entry in the write buffer are cache misses.

6. The processor as recited in claim 4 , wherein the write buffer is configured to request that a cache line be resent responsive to determining a corresponding fill has come back with an error.

7. A method for use in a processor comprising:
storing a first store instruction in a first entry of a store queue comprising a plurality of entries; and
storing a second store instruction in a second entry of the store queue of a processor,
wherein the first store instruction is older than the second store instruction,
wherein each entry of the store queue each entry stores:
an identification of a store instruction;
an indication as to whether the store instruction is speculative or non-speculative; and
a pending miss request indicator which indicates, in response to a cache hit, that data targeted by the store instruction is available in a cache;

in response to determining the second store instruction is ready to commit to a memory hierarchy:
allowing the second store instruction to commit before the first store instruction, in response to determining:
an indication in the second entry indicates the second store instruction is non-speculative; and
a pending miss indicator in the second entry indicates data targeted by the second instruction is available in the cache; and

preventing the second store instruction from committing to the memory hierarchy before the first store instruction, in response to determining that at least one store instruction in the store queue older than the second store instruction is speculative.

8. The method as recited in claim 7 , wherein store instructions in the store queue that are speculative are subject to being flushed, and store instructions in the store queue that are non-speculative are not subject to being flushed.

9. The method as recited in claim 7 , wherein an indication in an entry of the store queue indicates a corresponding store instruction is non-speculative in response to a determination that all older stores to a same address as the store instruction are complete, all older loads are complete, all older barrier instructions are complete, and all older branch instructions are resolved.

10. The method as recited in claim 7 , further comprising:
moving the first and second store instructions from the store queue to a write buffer when the first and second store instructions become non-speculative;
committing the second store instruction to a cache from the write buffer responsive to determining the second store instruction is a cache hit; and
delaying committing the first store instruction to the cache from the write buffer responsive to determining the first store instruction is a cache miss.

11. The method as recited in claim 10 , further comprising preventing a non-speculative store instruction from moving from the store queue to the write buffer responsive to determining both a youngest entry and an oldest entry in the write buffer are cache misses.

12. The method as recited in claim 10 , further comprising requesting, by the write buffer, that a cache line be resent responsive to determining a corresponding fill has come back with an error.

13. A computing system comprising:
a memory; and
a processor comprising:
a cache configured to store data retrieved from the memory; and
a store queue comprising a plurality of entries, wherein each entry stores:
an identification of a store instruction;
an indication as to whether the store instruction is speculative or non-speculative; and
a pending miss request indicator which indicates, in response to a cache hit, that data targeted by the store instruction is available in a cache;

wherein the processor is configured to:
store a first store instruction in a first entry of the store queue; and
store a second store instruction in a second entry of the store queue, wherein the first store instruction is older than the second store instruction; and

in response to determining the second store instruction is ready to commit to a memory hierarchy, the processor is configured to:
allow the second store instruction to commit before the first store instruction, in response to determining:
an indication in the second entry indicates the second store instruction is non-speculative; and
a pending miss indicator in the second entry indicates data targeted by the second instruction is available in the cache;

prevent the second store instruction from committing to the memory hierarchy before the first store instruction, in response to determining that at least one store instruction in the store queue older than the second store instruction is speculative.

14. The computing system as recited in claim 13 , wherein store instructions in the store queue that are speculative are subject to being flushed, and

Assignees

• Apple Inc

Inventors

• Kothari Kulin N
• Agarwal Mridul
• Kanapathipillai Pradeep

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3834 Primary

  Maintaining memory consistency · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/3855

  Physics · mapped topic