Architected state retention for a frequent operating state switching processor

Patent metadata

Field	Value
Publication number	US-10990159-B2
Application number	US-201715496290-A
Country	US
Kind code	B2
Filing date	Apr 25, 2017
Priority date	Apr 25, 2017
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.

First claim

What is claimed is:

1. A processor comprising:
a memory interface configured to access off-chip memory;
a core configured to process instructions;
a plurality of on-die storage elements configured to store architected state information of the processor, wherein a first subset of the plurality of on-die storage elements comprises retention logic configured to store a copy of architected state information stored within the given on-die storage element, concurrent with storage of the architected state information in the given on-die storage element and prior to detection of an indication to transition from a processor active state to a processor sleep state; and
control logic configured to, based at least in part on the detection of the indication to transition from the processor active state to the processor sleep state:
retain a copy of architected state information stored within the first subset of the plurality of on-die storage elements, without retaining architected state information stored in a second subset of the plurality of on-die storage elements in any of the plurality of on-die storage elements and the off-chip memory; and
transition the processor to the processor sleep state.

2. The processor as recited in claim 1 , wherein based at least in part on a detection of an indication to transition from the processor sleep state to the processor active state, the control logic is configured to retrieve the copy of the architected state information from the first subset of the plurality of on-die storage elements to restore the architected state information.

3. The processor as recited in claim 2 , wherein the control logic is further configured to initialize data for storage in the second subset of the plurality of on-die storage elements to restore the architected state information.

4. The processor as recited in claim 2 , wherein the control logic is further configured to fetch an instruction from a memory location pointed to by a restored program counter of the architected state information rather than from a memory location pointed to by a reset base address register.

5. The processor as recited in claim 1 , wherein based at least in part on a detection of an access request for the architected state information while the processor is in the processor sleep state, the control logic is further configured to:
power up at least a first portion of the processor; and
identify one or more of the first subset of the plurality of on-die storage elements storing a given subset of the architected state information specified in the access request.

6. The processor as recited in claim 5 , wherein based at least in part on a detection that the access request is a read request, the control logic is further configured to:
send a copy of the given subset of the architected state information from the one or more of the first subset of the plurality of on-die storage elements as a response to the access request; and
power down the first portion of the processor.

7. The processor as recited in claim 5 , wherein the control logic is further configured to, based at least in part on a detection that the access request is a write request:
update the given subset of the architected state information in the one or more of the first subset of the plurality of on-die storage elements with write data; and
power down the first portion of the processor.

8. A method comprising:
accessing, by a memory interface, off-chip memory;
processing, by a core, instructions;
storing, by control logic, architected state information of the processor in a plurality of on-die storage elements, wherein a first subset of the on-die storage elements comprises retention logic
that stores a copy of architected state information stored within the given on-die storage element, concurrent with storage of the architected state information in the given on-die storage element and prior to detection of an indication to transition from a processor active state to a processor sleep state; and
in response to detecting the indication to transition from the processor active state to the processor sleep state:
retaining, by control logic, a copy of architected state information stored within the first subset of the plurality of on-die storage elements, without retaining architected state information stored in a second subset of the plurality of on-die storage elements in any of the plurality of on-die storage elements and the off-chip memory; and
transitioning, by the control logic, the processor to the processor sleep state.

9. The method as recited in claim 8 , further comprising retrieving the copy of the architected state information from the first subset of the plurality of on-die storage elements to restore the architected state information, in response to detecting an indication to transition from the processor sleep state to the processor active state.

10. The method as recited in claim 9 , further comprising initializing data for storage in the second subset of the plurality of on-die storage elements to restore the architected state information.

11. The method as recited in claim 9 , further comprising fetching an instruction from a memory location pointed to by a restored program counter of the architected state information rather than from a memory location pointed to by a reset base address register.

12. The method as recited in claim 9 , further comprising foregoing a boot sequence.

13. The method as recited in claim 9 , further comprising supplying a first voltage to the retention logic of the first subset of the plurality of on-die storage elements that is less than a second voltage supplied to the second subset of the plurality of on-die storage elements during the processor active state.

14. The method as recited in claim 8 , wherein in response to detecting an access request for the architected state information while the processor is in the processor sleep state, the method further comprises:
powering up at least a first portion of the processor; and
identifying one or more of the first subset of the plurality of on-die storage elements storing a given subset of the architected state information specified in the access request.

15. The method as recited in claim 14 , wherein in response to detecting the access request is a read request, the method further comprises:
sending a copy of the given subset of the architected state information from the one or more of the first subset of the plurality of on-die storage elements as a response to the access request; and
powering down the first portion of the processor.

16. The method as recited in claim 14 , further comprising, in response to detecting the access request is a write request:
updating the given subset of the architected state information in the one or more of the first subset of the plurality of on-die storage elements with write data; and
powering down the first portion of the processor.

17. A computing system comprising:
a memory;
a processor configured to:
process instructions;
store architected state information of the processor in a plurality of on-die storage elements, wherein a first subset of the on-die storage elements comprises retention logic
configured to store a copy of architected state information stored within the given on-die storage element, concurrent with storage of the architected state information in the given on-die storage element and prior to detection of an indication to transition from a processor active state to a processor sleep state; and
in response to detecting the indication to transiti

Assignees

• Apple Inc

Inventors

• Semeria Bernard Joseph
• Mylius John H
• Kanapathipillai Pradeep
• Russo Richard F
• Wen Shih-Chieh
• Larson Richard H

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/3802

  Instruction prefetching · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title