Processors including power control circuits to reduce a no-load voltage to save power and increase longevity and related methods

Patent metadata

Field	Value
Publication number	US-12468377-B2
Application number	US-202318469890-A
Country	US
Kind code	B2
Filing date	Sep 19, 2023
Priority date	Sep 19, 2023
Publication date	Nov 11, 2025
Grant date	Nov 11, 2025

Abstract

Power sources provide power in a range with a maximum supply voltage provided under zero-load current conditions. Power circuits in an IC receive and aggregate indications of load current from processor circuits in processor circuit clusters and, reduce power consumption in the IC during zero or low load current conditions by generating a voltage control signal to reduce the supply voltage. Reducing the no-load voltage also reduces stress on gate oxides of transistors in the IC to increase oxide longevity. Based on the aggregated load current indications, which is periodically updated, the no-load supply voltage may be incrementally reduced down to a voltage threshold over the course of multiple periods. In some examples, the power circuits receive throttle signals when the processor circuits are throttled due to a voltage droop, and such signals may cause the power circuits to generate a control signal to increase the no-load voltage.

First claim

What is claimed is:

1 . An integrated circuit (IC) comprising:
at least one cluster, each cluster comprising:
at least one processor circuit; and
a cluster power circuit configured to receive, from each of the at least one processor circuit, an indication of load current;
a power rail configured to provide power at a supply voltage in a supply voltage range to the at least one processor circuit in the at least one cluster, wherein the supply voltage range comprises a no-load voltage in response to zero-load current on the power rail; and a processor power circuit configured to:
receive, from the cluster power circuit in each of the at least one cluster, an aggregation of the indication of load current received from each of the at least one processor circuit; and
in response to the aggregation of the indication of load current from each of the at least one cluster comprising an indication of load current lower than a first current threshold, generate a voltage control signal to reduce the no-load voltage.

2 . The IC of claim 1 , wherein the processor power circuit is configured to generate the voltage control signal to reduce the no-load voltage in response to the aggregation of the indication of load current from each of the at least one cluster comprising only indications of load current lower than the first current threshold.

3 . The IC of claim 1 , wherein each of the at least one processor circuit in each of the at least one cluster comprises:
a voltage sensor configured to sense the supply voltage on the power rail; and a throttler configured to, in response to the voltage sensor sensing the supply voltage below a first voltage threshold:
reduce a rate of power consumption in the at least one processor circuit; and
generate a first throttle signal.

4 . The IC of claim 3 , wherein the cluster power circuit in each of the at least one cluster is further configured to:
receive the first throttle signal from each of the at least one processor circuit in the cluster; and generate a second throttle signal in response to receiving the first throttle signal from any one of the at least one processor circuit in the cluster.

5 . The IC of claim 1 , wherein:
the cluster power circuit is further configured to:
receive the indication of load current from each of the at least one processor circuit periodically, in each period of length N; and
the processor power circuit is further configured to:
receive the aggregation of the indication of load current from the cluster power circuit in each of the at least one cluster periodically, in each period of length M, where M is greater than N; and
generate the voltage control signal to reduce the no-load voltage in each period of length M based on the aggregation of the indication of load current from the cluster power circuit in each of the at least one cluster.

6 . The IC of claim 1 , wherein:
the processor power circuit is further configured to generate the voltage control signal to reduce the no-load voltage by a first voltage increment.

7 . The IC of claim 3 , wherein:
the processor power circuit is further configured to generate the voltage control signal to reduce the no-load voltage in response to the no-load voltage being above a second voltage threshold.

8 . The IC of claim 4 , wherein:
the processor power circuit is further configured to generate the voltage control signal to increase the no-load voltage provided to the power rail in response to the second throttle signal.

9 . The IC of claim 8 , wherein:
the processor power circuit is further configured to generate the voltage control signal to increase the no-load voltage by a second voltage increment based on a difference between a first voltage and the no-load voltage.

10 . The IC of claim 9 , wherein:
the processor power circuit is further configured to generate the voltage control signal to increase the no-load voltage based on a percentage of the difference between the first voltage and the no-load voltage.

11 . The IC of claim 3 , wherein the first voltage threshold corresponds to a voltage threshold of a transistor in the at least one processor circuit.

12 . The IC of claim 1 , wherein:
the cluster power circuit in the at least one cluster is configured to provide, to the processor power circuit, an indication of leakage current in the at least one processor circuit; and the processor power circuit is configured to generate the voltage control signal to the power source to provide power to the power rail based on the indication of leakage current and the aggregation of the indication of load current from the cluster power circuit in the at least one cluster.

13 . The IC of claim 3 , wherein the throttler is further configured to increase a period of a clock cycle of a clock provided to the at least one processor circuit.

14 . The IC of claim 1 , wherein the processor power circuit is configured to generate the voltage control signal to maintain the no-load voltage in response to the aggregation of the indication of load current from the at least one cluster comprising at least one indication of a load current exceeding the first current threshold.

15 . The IC of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.

16 . A method in an integrated circuit (IC) comprising at least one processor circuit in each of at least one cluster, the method comprising:
receiving, in a cluster power circuit in each of the at least one cluster, an indication of load current from each of the at least one processor circuit; receiving, in the at least one processor circuit in the at least one cluster, power from a power source on a power rail at a supply voltage in a supply voltage range to, wherein the supply voltage range comprises a no-load voltage provided in response to zero-load current on the power rail; receiving, from the cluster power circuit in each of the at least one cluster, an aggregation of the indication of load current received from each of the at least one processor circuit; and in response to the aggregation of the indication of load current received from each of the at least one cluster comprising indications of load current lower than a first current threshold, generating a voltage control signal to reduce the no-load voltage.

17 . The method of claim 16 , further comprising generating the voltage control signal to reduce the no-load voltage in response to the aggregation of the indication of load current from each of the at least one cluster comprising only indications of load current lower than the first current threshold.

18 . The method of claim 16 , further comprising, in each of the at least one processor circuit in each of the at least one cluster:
sensing the supply volta

Assignees

• Qualcomm Inc

Inventors

• Nemani Mahadevamurty
• Baraka Ravi Adarsh
• Makhija Nitin
• Kanapathipillai Pradeep

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title