Unified address translation

Patent metadata

Field	Value
Publication number	US-11221962-B2
Application number	US-202016874997-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	Sep 4, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

First claim

What is claimed is:

1. An apparatus comprising:
an address translation unit; and
a memory;
wherein in response to receiving a memory access operation comprising a first address, the address translation unit is configured to:
search a lookup table using a permission index corresponding to the first address to identify a data access permission stored in the lookup table, wherein the permission index is shared by the apparatus and an external processing unit; and
access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission;

wherein:
an address mapping between the first address and the second address is shared by the apparatus and an external processing unit; and
the external processing unit uses a different data access permission than the identified data access permission.

2. The apparatus as recited in claim 1 , wherein the address translation unit is configured to determine the permission index and the second address based on the first address.

3. The apparatus as recited in claim 2 , wherein the address translation unit is further configured to distinguish among a plurality of types of data access permissions for the same permission index based on an operating mode of the apparatus.

4. The apparatus as recited in claim 2 , wherein the address translation unit is further configured to distinguish among a plurality of types of data access permissions for the same permission index using an exception level of the apparatus.

5. The apparatus as recited in claim 1 , wherein the data access permission of the apparatus does not comprise execute permission and the data access permission of the external processing unit does comprise execute permission.

6. The apparatus as recited in claim 1 , wherein a copy of each of the permission index and the address mapping between the first address and the second address is stored in a shared page table in external memory.

7. A method, comprising:
receiving, by a processor complex, a memory access operation comprising a first address targeting a memory; and
in response to receiving the memory access operation:
searching, by an address translation unit of the processor complex, a lookup table using a permission index corresponding to the first address to identify a data access permission stored in the lookup table; and
accessing, by the address translation unit, data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission;

wherein the permission index and an address mapping between the first address and the second address are shared by the processor complex and an external processing unit, wherein the external processing unit uses a different data access permission than the identified data access permission.

8. The method as recited in claim 7 , further comprising the address translation unit determining the permission index and the second address based on the first address.

9. The method as recited in claim 8 , further comprising distinguishing among a plurality of data access permissions for the same permission index based on an operating mode of the processor complex.

10. The method as recited in claim 8 , further comprising distinguishing among a plurality of data access permissions for the same permission index based on an exception level of the processor complex.

11. The method as recited in claim 7 , wherein the data access permission of the processor complex does not comprise an execute permission and the data access permission of the external processing unit does comprise an execute permission.

12. The method as recited in claim 7 , wherein a copy of each of the permission index and the address mapping between the first address and the second address is stored in a shared page table in external memory.

13. A non-transitory computer readable storage medium storing program instructions, wherein the program instructions are executable by a processor to:
receive a memory access operation comprising a first address targeting a memory; and
in response to receiving the memory access operation:
search a lookup table using a permission index corresponding to the first address to identify a data access permission stored in the lookup table; and
access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission;

wherein the permission index and an address mapping between the first address and the second address are shared by the processor and an external processing unit, wherein the external processing unit uses a different data access permission than the identified data access permission.

14. The non-transitory computer readable storage medium as recited in claim 13 , wherein the program instructions are executable by a processor to determine the permission index and the second address based on the first address.

15. The non-transitory computer readable storage medium as recited in claim 14 , wherein the program instructions are executable by the processor to distinguish among a plurality of data access permissions for the same permission index based on an operating mode of the processor.

16. The non-transitory computer readable storage medium as recited in claim 14 , wherein the program instructions are executable by the processor to distinguish among a plurality of types of data access permissions for the same permission index based on an exception level of the processor.

17. The non-transitory computer readable storage medium as recited in claim 13 , wherein a copy of each of the permission index and the address mapping between the first address and the second address is stored in a shared page table in external memory.

Assignees

• Apple Inc

Inventors

• Gonion Jeffry E
• Semeria Bernard Joseph
• Swift Michael J
• Kanapathipillai Pradeep
• Williamson David J

Classifications

• G06F12/1475

  in a virtual system, e.g. with translation means · CPC title

• G06F12/0873

  Mapping of cache memory to specific storage devices or parts thereof · CPC title

• G06F12/1036

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F12/1072

  Decentralised address translation, e.g. in distributed shared memory systems · CPC title