Dynamic voltage and frequency scaling (DVFS) within processor clusters

Patent metadata

Field	Value
Publication number	US-11797045-B2
Application number	US-202217666420-A
Country	US
Kind code	B2
Filing date	Feb 7, 2022
Priority date	Sep 22, 2021
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster. In some implementations, the power management processor receives, from a system controller external to the plurality of processing clusters, a first power allocation for the first processing cluster.

First claim

What is claimed is:

1. A method, comprising:
at a first processing cluster with a plurality of processors and a power management controller distinct from the plurality of processors, the first processing cluster is included in an electronic device:
obtaining performance information about the plurality of processors;
executing first instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state, different from the first performance state, in accordance with the obtained performance information, independently of respective performance states of other processors in the plurality of processors; and
executing one or more debug instructions to perform debugging of a respective processor of the plurality of processors,

wherein the electronic device includes a plurality of processing clusters including the first processing cluster, further comprising:
receiving, from a system controller that is distinct from the plurality of processing clusters, a first power allocation for the first processing cluster; and
assigning respective performance states to the plurality of processors, including the first processor, in accordance with the first power allocation for the first processing cluster,

wherein the performance information includes activity levels, energy consumption, temperature measurements, counts of performance limit breaches, and/or throttling instructions for one or more of the plurality of processors, and
wherein, in accordance with the performance information indicating an increase in a temperature of the first processor, the second performance state is a state that is associated with lower power consumption than the first performance state.

2. The method of claim 1 , wherein transitioning the first processor from the first performance state to the second performance state includes modifying a voltage provided to the first processor independently of respective voltages provided to other processors in the plurality of processors.

3. The method of claim 1 , wherein transitioning the first processor from the first performance state to the second performance state includes modifying a clock frequency of the first processor independently of respective clock frequencies of other processors in the plurality of processors.

4. The method of claim 1 , further comprising:
executing second instructions to transition a second processor of the plurality of processors from a third performance state to a fourth performance state in accordance with the obtained performance information, independently of respective performance states of other processors in the plurality of processors.

5. The method of claim 1 , further comprising:
assigning the respective performance states to the plurality of processors in accordance with the first power allocation such that aggregate power consumption of the plurality of processors in the first processing cluster does not exceed the first power allocation.

6. The method of claim 1 , wherein:
a first amount of time is between a time corresponding to the power management processor obtaining the performance information and a time corresponding to the first processor transitioning from the first performance state to the second performance state in response to the power management processor executing the first instructions to transition performance state of the first processor;
a second amount of time is between a time corresponding to the system controller obtaining the performance information and a time corresponding to the first processor transitioning from the first performance state to the second performance state in response to the system controller executing instructions to transition performance state of the first processor; and
the first amount of time is less than the second amount of time.

7. The method of claim 1 , further comprising:
receiving, from the system controller, a second power allocation for the first processing cluster, wherein the second power allocation is different from the first power allocation;
determining respective performance states of the plurality of processors in accordance with the second power allocation, wherein the determined respective performance state of the first processor is different from the second performance state; and
executing instructions to transition the plurality of processors to the respective performance states, including executing instructions to transition the first processor from the second performance state to the determined respective performance state.

8. The method of claim 1 , wherein, in accordance with the performance information indicating a respective number of performance limit breaches in a respective time period that exceeds a threshold number of performance limit breaches for the respective time period, the second performance state is a state that is associated with lower power consumption than the first performance state.

9. The method of claim 1 , wherein, in accordance with the performance information indicating a third processor of the plurality of processors, different from the first processor, transitioning from an off state to an on state, the second performance state is a state that is associated with lower power consumption than the first performance state.

10. The method of claim 1 , wherein, in accordance with the performance information indicating a fourth processor of the plurality of processors, different from the first processor, transitioning from an on state to an off state, the second performance state is a state that is associated with higher power consumption than the first performance state.

11. The method of claim 1 , further comprising:
executing the one or more debug instructions to perform debugging of the respective processor of the plurality of processors while the respective processor executes application instructions.

12. The method of claim 1 , wherein the one or more debug instructions are executed to perform debugging of the first processor when the first processor operates at the second performance state.

13. The method of claim 1 , further comprising:
initializing one or more settings for the plurality of processors by modifying a default hardware state of the device prior to the plurality of processors executing application instructions.

14. The method of claim 1 , wherein the first processing cluster includes a cache coupled to one or more of the plurality of processors in the first processing cluster, the method further comprising:
performing the debugging of the respective processor using the cache of the first processing cluster.

15. The method of claim 1 , further comprising:
communicating with power management circuitry having one or more voltage regulators that supply power to the device.

16. An electronic device, comprising:
a first processing cluster, including:
a plurality of processors; and
a power management processor distinct from the plurality of processors;

wherein the power management processor is configured to:
obtain performance information about the plurality of processors;
execute first instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state, different from the first performance state, in accordance with the obtained performance information, independently of respective performance states of other processors in the plurality of processors; and
execute one or more debug instructions to perform debugging of a respective processor of the plurality of processors; and

a syste

Assignees

• Qualcomm Inc

Inventors

• Masters Jonathan
• Kanapathipillai Pradeep
• Gulati Manu
• Makhija Nitin

Classifications

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• G06F11/3409 Primary

  for performance assessment · CPC title