Graphics processing unit processing and caching improvements
US-12572997-B2 · Mar 10, 2026 · US
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Janus Scott patents
Janus Scott is listed as an inventor on 135 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Janus Scott |
| Total patents | 135 |
| First publication | Mar 31, 2015 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Multi-tile memory management
US-12554674-B2 · Feb 17, 2026 · US
Graphics processing unit processing and caching improvements
US-12493922-B2 · Dec 9, 2025 · US
Multi-plane image compression
US-12450780-B2 · Oct 21, 2025 · US
Graphics architecture including a neural network pipeline
US-2025252650-A1 · Aug 7, 2025 · US
Anti-cheat game technology in graphics hardware
US-12370453-B2 · Jul 29, 2025 · US
Sparse optimizations for a matrix accelerator architecture
US-2025209564-A1 · Jun 26, 2025 · US
Glare and occluded view compensation for automotive and other applications
US-2025182709-A1 · Jun 5, 2025 · US
Sparse optimizations for a matrix accelerator architecture
US-12293431-B2 · May 6, 2025 · US
Multi-tile memory management
US-2025117356-A1 · Apr 10, 2025 · US
Recent patents
Latest publications not already listed above.
Systems and methods for improving cache efficiency and utilization
US-2025103548-A1 · Mar 27, 2025 · US
Systems and methods for cache optimization
US-2025103511-A1 · Mar 27, 2025 · US
Systems and methods for error detection and control for embedded memory and compute elements
US-2025103430-A1 · Mar 27, 2025 · US
Glare and occluded view compensation for automotive and other applications
US-12243496-B2 · Mar 4, 2025 · US
Method and apparatus of spatially sparse convolution module for visual rendering and synthesis
US-2025061172-A1 · Feb 20, 2025 · US
Graphics architecture including a neural network pipeline
US-12229867-B2 · Feb 18, 2025 · US
Multi-tile graphics processor rendering
US-2025046001-A1 · Feb 6, 2025 · US
Systems and methods for improving cache efficiency and utilization
US-12210477-B2 · Jan 28, 2025 · US
Graphics processor operation scheduling for deterministic latency
US-2025028675-A1 · Jan 23, 2025 · US
Multi-tile memory management
US-2025004981-A1 · Jan 2, 2025 · US
Multi-tile memory management
US-12182062-B1 · Dec 31, 2024 · US
Systems and methods for cache optimization
US-12182035-B2 · Dec 31, 2024 · US
Systems and methods for error detection and control for embedded memory and compute elements
US-12147302-B2 · Nov 19, 2024 · US
Method and apparatus of spatially sparse convolution module for visual rendering and synthesis
US-12124533-B2 · Oct 22, 2024 · US
Systems and methods for cache optimization
US-12124383-B2 · Oct 22, 2024 · US
Multi-tile architecture for graphics operations
US-2024320184-A1 · Sep 26, 2024 · US
Multi-tile memory management
US-12099461-B2 · Sep 24, 2024 · US
Multi-tile graphics processor rendering
US-12094048-B2 · Sep 17, 2024 · US
Graphics processor operation scheduling for deterministic latency
US-12079155-B2 · Sep 3, 2024 · US
Systems and methods for cache optimization
US-12056059-B2 · Aug 6, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 135 |
| Janus Scott | 6 |
| Martin Jason | 2 |
| Cheng Scott W | 2 |
| Chhabra Siddhartha | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06T1/20 | 91 |
| G06T1/60 | 70 |
| G06N3/0464 | 49 |
| G06N3/09 | 41 |
| G06T15/005 | 41 |