Systems and methods for cache optimization

Patent metadata

Field	Value
Publication number	US-12182035-B2
Application number	US-202017428529-A
Country	US
Kind code	B2
Filing date	Mar 14, 2020
Priority date	Mar 15, 2019
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

First claim

What is claimed is:

1. A graphics processor, comprising:
processing resources to perform graphics operations; and
a cache controller of a cache of the graphics processor coupled to the processing resources, the cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint at an instruction level having attributes to indicate a direction level of aging allocation to modify an age level of the aging field to improve a caching policy has been received.

2. The graphics processor of claim 1 , wherein the cache controller is further configured to modify an aging policy when the hint at an instruction level sets a higher level age allocation for a first graphics surface and a lower level age allocation for a second graphics surface based on user level exposure.

3. The graphics processor of claim 1 , wherein the initial aging policy comprises a least recently used data or cache line policy.

4. The graphics processor of claim 1 , wherein the modified aging policy comprises a combination of age and level of importance as provided via user level exposure.

5. The graphics processor of claim 4 , wherein the level of importance includes a first level of importance to preserve data longer in the cache for a first time period.

6. The graphics processor of claim 4 , wherein the level of importance includes a second level of importance for data to be evicted from the cache within a second time period, which is less than the first time period.

7. The graphics processor of claim 4 , wherein the modified aging policy comprises a combination of age and level of importance including a multi-bit cache policy.

8. The graphics processor of claim 4 , wherein the cache controller is configured to modify the aging policy by modifying age or level of importance based on the received hint or instruction.

9. A computer implemented method, comprising:
initializing, with a cache controller, cache memory with allocated cache lines;
setting an initial aging policy using an aging field based on age of each cache line within the cache memory; and
determining, with the cache controller, whether a hint at an instruction level having attributes to indicate a level of aging to modify an age level of the aging field to improve a caching policy has been received.

10. The computer implemented method of claim 9 , further comprising:
implementing the initial aging policy using age of cache lines if no hint or instruction with attributes has been received.

11. The computer implemented method of claim 9 , further comprising:
modifying, with the cache controller, the initial aging policy when the hint or the instruction having attributes is received.

12. The computer implemented method of claim 11 , wherein the modified aging policy comprises a combination of age and level of importance as provided via user level exposure.

13. The computer implemented method of claim 12 , wherein a first cache line has a first age level setting, a second cache line has a second age level setting, and a third cache line has a third age level setting.

14. The computer implemented method of claim 13 , wherein the third age level setting has a lowest age level setting causing an entry from the third cache line to be evicted.

15. The computer implemented method of claim 13 , wherein the first age level setting is downgraded to the second age level setting and the second age level setting is downgraded to the third age level setting when the entry for the third cache line is evicted.

16. A cache memory of a graphics processing unit (GPU), comprising:
a data array to store data; and
a cache controller of the GPU coupled to the data array, the cache controller is configured to set an initial aging policy using an aging field based on age of data within the data array and to determine whether a hint at an instruction level to indicate a level of aging to modify an age level of the aging field to improve a caching policy has been received.

17. The cache memory of claim 16 , wherein the cache controller is further configured to modify an aging policy when the hint at an instruction level sets a higher level age allocation for a first graphics surface and a lower level age allocation for a second graphics surface based on user level exposure.

18. The cache memory of claim 16 , wherein the initial aging policy comprises a least recently used data or cache line policy.

19. The cache memory of claim 17 , wherein the modified aging policy comprises a combination of age and level of importance as provided via user level exposure.

20. The cache memory of claim 19 , wherein the level of importance includes a first level of importance to preserve data longer in the cache for a first time period.

21. The cache memory of claim 20 , wherein the level of importance includes a second level of importance for data to be evicted from the cache within a second time period, which is less than the first time period.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Ray Joydeep
• Ould-Ahmed-Vall Elmoustapha
• Appu Abhishek
• Anantaraman Aravindh
• Andrei Valentin
• Bilagi Durgaprasad
• George Varghese
• Insko Brent
• Jahagirdar Sanjeev
• Janus Scott
• K Pattabhiraman
• Kim Sungye
• Maiyuran Subramaniam
• Ranganathan Vasanth
• Striramassarma Lakshminarayanan
• Tian Xinmin

Classifications

• G06T1/60

  Memory management · CPC title

• G06F2212/302

  In image processor or graphics adapter · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title