Multi-tile architecture for graphics operations

Patent metadata

Field	Value
Publication number	US-2024320184-A1
Application number	US-202418620284-A
Country	US
Kind code	A1
Filing date	Mar 28, 2024
Priority date	Mar 15, 2019
Publication date	Sep 26, 2024
Grant date	—

Abstract

Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

First claim

1 - 20 . (canceled)

21 . An apparatus comprising:
a multi-tile architecture for graphics operations including a graphics processing unit (GPU, the GPU including:
a plurality of processing core tiles installed on one or more dies, and
a plurality of fixed function units to perform certain processing functions;
wherein the apparatus is to: receive one or more applications for performance by the GPU; analyze processing requirements for the one or more applications; determine a preferred assignment of the plurality of fixed function units to the plurality of processing core tiles based at least in part on the processing requirements for the one or more applications; and provide a dynamic exclusive assignment of one or more of the fixed function units to one or more of the processing core tiles according to the determined preferred assignment.

22 . The apparatus of claim 21 , wherein determining the preferred assignment of the plurality of fixed function units to the plurality of processing core tiles includes optimizing power and performance characteristics for processing of the one or more applications.

23 . The apparatus of claim 21 , wherein a first fixed function unit includes one or more performance characteristics that differ from one or more performance characteristics of a second fixed function unit.

24 . The apparatus of claim 23 , wherein the one or more performance characteristics include one or more of performance speed and power consumption.

25 . The apparatus of claim 21 , wherein the apparatus is further to modify the dynamic assignment of the fixed function units to the processing core tiles in response to one or more changes in processing requirements.

26 . The apparatus of claim 21 , wherein the GPU further includes a structure to interconnect the plurality of processing core tiles with the plurality of fixed function units.

27 . The apparatus of claim 21 , wherein the one or more applications include one or more shader programs.

28 . A method comprising:
receiving one or more applications for performance by a graphics processing unit (GPU), the GPU including a plurality of processing core tiles and a plurality of fixed function units; analyzing processing requirements for the one or more applications; determining a preferred assignment of the plurality of fixed function units to the plurality of processing core tiles based at least in part on the processing requirements for the one or more applications; and providing a dynamic exclusive assignment of one or more of the fixed function units to one or more of the processing core tiles according to the determined preferred assignment.

29 . The method of claim 28 , wherein determining the preferred assignment of the plurality of fixed function units to the plurality of processing core tiles includes optimizing power and performance characteristics for processing of the one or more applications.

30 . The method of claim 28 , wherein a first fixed function unit includes one or more performance characteristics that differ from one or more performance characteristics of a second fixed function unit.

31 . The method of claim 30 , wherein the one or more performance characteristics include one or more of performance speed and power consumption.

32 . The method of claim 28 , further comprising:
modifying the dynamic assignment of the fixed function units to the processing core tiles in response to one or more changes in processing requirements.

33 . The method of claim 28 , wherein the one or more applications include one or more shader programs.

34 . A system comprising:
one or more processors including a multi-tile graphics processing unit (GPU); and a memory to hold data for processing; wherein the multi-tile GPU includes:
a plurality of processing core tiles installed on one or more dies, and
a plurality of fixed function units to perform certain processing functions; and
wherein the one or more processors are to: receive one or more applications for performance by the multi-tile GPU; analyze processing requirements for the one or more applications; determine a preferred assignment of the plurality of fixed function units to the plurality of processing core tiles based at least in part on the processing requirements for the one or more applications; and provide a dynamic exclusive assignment of one or more of the fixed function units to one or more of the processing core tiles according to the determined preferred assignment.

35 . The system of claim 34 , wherein determining the preferred assignment of the plurality of fixed function units to the plurality of processing core tiles includes optimizing power and performance characteristics for processing of the one or more applications.

36 . The system of claim 34 , wherein a first fixed function unit includes one or more performance characteristics that differ from one or more performance characteristics of a second fixed function unit.

37 . The system of claim 36 , wherein the one or more performance characteristics include one or more of performance speed and power consumption.

38 . The system of claim 37 , wherein the one or more processors are further to modify the dynamic assignment of the fixed function units to the processing core tiles in response to one or more changes in processing requirements.

39 . The system of claim 35 , wherein the multi-tile GPU further includes a structure to interconnect the plurality of processing core tiles with the plurality of fixed function units.

40 . The system of claim 35 , wherein the one or more applications include one or more shader programs.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Ashbaugh Ben
• Janus Scott
• Anantaraman Aravindh
• Appu Abhishek R
• Cooray Niranjan
• George Varghese
• Hunter Arthur
• Insko Brent E
• Ould-Ahmed-Vall Elmoustapha
• Panneer Selvakumar
• Ranganathan Vasanth
• Ray Joydeep
• Sinha Kamal
• Striramassarma Lakshminarayanan
• Surti Prasoonkumar
• Tangri Saurabh

Classifications

• G06F2212/652

  Page size control · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F2212/6026

  Prefetching based on access pattern detection, e.g. stride based prefetch · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title