Systems and methods for error detection and control for embedded memory and compute elements

Patent metadata

Field	Value
Publication number	US-12147302-B2
Application number	US-202017095530-A
Country	US
Kind code	B2
Filing date	Nov 11, 2020
Priority date	Nov 15, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

First claim

What is claimed is:

1. A graphics multiprocessor, comprising:
memory of the graphics multiprocessor for storing data, wherein the memory is cache or local memory; and
error detection correction circuitry having error registers and integrated with the memory of the graphics multiprocessor, the error detection correction circuitry is configured to perform a tag read of the memory to determine whether error detection correction information of error detection and correction logic indicates an error condition or not, and to report the error condition to the error registers to log a source of a correctable error when a correctable error occurs or to report the error condition to the error registers to report an uncorrectable error when an uncorrectable error occurs, wherein the error detection correction circuitry is located on chip or on die with the graphics multiprocessor.

2. The graphics multiprocessor of claim 1 , wherein the error detection correction information comprises parity information or a single-error-detecting code.

3. The graphics multiprocessor of claim 2 , wherein the error detection correction circuitry is further configured to determine whether the parity information or the single-error-detecting code indicates an error condition or not.

4. The graphics multiprocessor of claim 3 , wherein the error detection correction circuitry is further configured to determine whether data of the cache or shared memory that is associated with the parity information is clean based on being modified in the cache or shared memory and also modified in main memory when the parity information indicates an error condition.

5. The graphics multiprocessor of claim 4 , wherein if the data that is associated with the parity information is not clean, then a fatal error condition is reported.

6. The graphics multiprocessor of claim 4 , wherein if the data that is associated with the parity information is clean, then the data is invalidated in the cache or local memory and the data is fetched from main memory.

7. The graphics multiprocessor of claim 1 , wherein the cache or local memory comprises an embedded dynamic random access memory (DRAM).

8. The graphics multiprocessor of claim 1 , wherein the memory comprises a first level cache or a second level cache having the error detection correction circuitry that is located on chip or on die with the graphics multiprocessor.

9. A computer implemented method for an error checking mechanism, comprising:
performing, with an error detection and correction logic of a memory of a graphics processing unit, a graphics multiprocessor, or a graphics processor, a tag read of the memory to check parity information of the tag; and
determining whether the parity information of the tag indicates an error condition or not, and to report the error condition to error registers of the error detection and correction logic to log a source of a correctable error when a correctable error occurs or to report the error condition to the error registers to report an uncorrectable error when an uncorrectable error occurs, wherein the memory is cache memory or shared memory, wherein the error detection correction circuitry is located on chip or on die with the graphics processing unit, the graphics multiprocessor, or the graphics processor.

10. The computer implemented method of claim 9 , further comprising:
determining whether data of the cache memory or shared memory that is associated with the parity information is clean based on being modified in the cache memory or shared memory and also modified in main memory when the parity information indicates an error condition.

11. The computer implemented method of claim 10 , wherein if the data that is associated with the parity information is not clean, then the uncorrectable error condition is reported.

12. The computer implemented method of claim 10 , further comprising:
invalidating the data in the cache or shared memory and fetching the data again from main memory when the data of the cache memory or shared memory that is associated with the parity information is clean and the parity information indicates the error condition.

13. A graphics processing unit (GPU) comprising:
cache memory of the GPU for storing data; and
error detection correction circuitry having error registers integrated with the cache memory of the GPU, the error detection correction circuitry is configured to perform a data error correction check at a predetermined granularity for data of the cache memory to check error information, and to report to the error registers to log a source of a correctable error when a correctable error occurs or to report an uncorrectable error to the error registers to report an uncorrectable error when an uncorrectable error occurs based on the error information, wherein the error detection correction circuitry is located on chip or on die with the graphics multiprocessor.

14. The GPU of claim 13 , wherein the error detection correction circuitry is on chip with the GPU.

15. The GPU of claim 14 , wherein detection of an uncorrected error or a corrected error does not change a load store pipeline functionality.

16. The GPU of claim 14 , wherein during Error Reporting the cache is coupled to the error registers for error logging and reporting including an uncorrectable error, a Data Correctable error, and a Tag parity error.

17. The GPU of claim 14 , wherein the error reporting is based on a type of error and a data error occurs during cache read or a cache eviction.

18. The GPU of claim 14 , wherein corrected errors are reported with program execution not being disrupted in any way.

19. The GPU of claim 16 , wherein the registers log a source of a corrected error including a first level cache data or a processing resource.

20. The GPU of claim 19 , wherein for uncorrectable errors (UCE), if an UCE is encountered during a data read including a cache read or a cache eviction, the data is returned to a processing resource but the error is also signaled to error registers.

Assignees

• Intel Corp

Inventors

• Ranganathan Vasanth
• Ray Joydeep
• Appu Abhishek R
• Kaburlasos Nikos
• Xu Lidong
• Maiyuran Subramaniam
• Koker Altug
• Matam Naveen
• Holland James
• Insko Brent
• Jahagirdar Sanjeev
• Janus Scott
• Bilagi Durgaprasad
• Tian Xinmin

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T1/60

  Memory management · CPC title

• G06F2212/70

  Details relating to dynamic memory management · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title