Systems and methods for improving cache efficiency and utilization

Patent metadata

Field	Value
Publication number	US-12210477-B2
Application number	US-202017428530-A
Country	US
Kind code	B2
Filing date	Mar 14, 2020
Priority date	Mar 15, 2019
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

First claim

What is claimed is:

1. A graphics processor, comprising:
processing resources to perform graphics operations; and
a cache controller of a cache of the graphics processor coupled to the processing resources, wherein the cache controller is configured to control cache priority by determining a default setting having a default cache attribute to be applied if no received instruction, determining whether an instruction from an application with an associated cache attribute has been received, and applying the instruction and the associated cache attribute when the instruction is received by the cache controller, wherein the cache controller is configured to receive the instruction including a store instruction having a write-streaming attribute to stream data for a streaming store that is cached with a low priority cache attribute in the cache.

2. The graphics processor of claim 1 , wherein the cache controller is configured to control cache priority with the default cache attribute having a lower priority than the instruction with the associated cache attribute.

3. The graphics processor of claim 2 , wherein the cache controller is configured to apply the instruction and associated cache attribute if the instruction has been received.

4. The graphics processor of claim 3 , wherein the cache controller applies the default cache attribute if an instruction has not been received.

5. The graphics processor of claim 1 , wherein the cache comprises a first level cache of the processing resources.

6. The graphics processor of claim 1 , wherein the associated cache attribute comprises no caching, write-through, write-back, or write-streaming for store or atomics operations.

7. The graphics processor of claim 1 , wherein the associated cache attribute comprises no caching, load caching, or load streaming for load or prefetch operations.

8. The graphics processor of claim 1 , wherein the data being streamed for a streaming store that is cached at low priority in the cache is evicted using a least recently used (LRU) position of the cache.

9. The graphics processor of claim 1 , wherein the cache controller is configured to receive a load message having an invalid after read attribute to invalidate data for a cache hit in the cache after a read operation if the data is from a private memory.

10. The graphics processor of claim 1 , wherein the cache controller is configured to receive a prefetch message having a load streaming attribute with data being streamed that is prefetched into the cache and given low priority, wherein the data being streamed is then evicted using a LRU position in the cache.

11. The graphics processor of claim 1 , wherein a least recently used (LRU) position of the cache is used to merge partial writes in the cache until a full cache line is generated based on a plurality of partial writes.

12. A method, comprising:
configuring a cache controller of a cache of a graphics processor to control cache priority between a default attribute and an instruction by determining a default setting having the default attribute to be applied if no received instruction;
determining whether the instruction with an associated cache attribute from an application has been received; and
determining whether the default attribute or the instruction with the associated cache attribute will control cache operations for the cache, wherein the cache controller is configured to receive the instruction including a load message having an invalid after read attribute to invalidate data for a cache hit in the cache after a read operation based on the data being from a private memory.

13. The method of claim 12 , further comprising:
applying the instruction and associated cache attribute if the instruction has been received.

14. The method of claim 13 , wherein the associated cache attribute comprises no caching, write-through, write-back, or write-streaming for store or atomics operations.

15. The method of claim 13 , wherein the associated cache attribute comprises no caching, load caching, or load streaming for load or prefetch operations.

16. The method of claim 12 , further comprising:
applying the default attribute if an instruction has not been received.

17. A graphics processing unit, comprising:
processing resources to perform graphics operations; and
a cache controller of a cache of the graphics processing unit coupled to the processing resources, wherein the cache controller is configured to control cache priority between a default attribute and an instruction with an associated cache attribute by determining a default setting having the default attribute to be applied if no received instruction, determining whether the instruction with an associated cache attribute has been received, and applying the instruction and the associated cache attribute when the instruction is received by the cache controller, wherein the cache controller is configured to receive the instruction including a prefetch message having a load streaming attribute with data being streamed that is prefetched into the cache and given low priority, wherein the data being streamed is then evicted using a least recently used (LRU) position in the cache.

18. The graphics processing unit of claim 17 , wherein the cache controller is configured to determine the default attribute having a lower priority and to determine whether the instruction has been received.

19. The graphics processing unit of claim 18 , wherein the cache controller applies the default attribute if an instruction has not been received.

20. The graphics processing unit of claim 17 , wherein the cache comprises a first level cache of the processing resources.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Ray Joydeep
• Ashbaugh Ben
• Pearce Jonathan
• Appu Abhishek
• Ranganathan Vasanth
• Striramassarma Lakshminarayanan
• Ould-Ahmed-Vall Elmoustapha
• Anantaraman Aravindh
• Andrei Valentin
• Galoppo Von Borries Nicolas
• George Varghese
• Harel Yoav
• Hunter Jr Arthur
• Insko Brent
• Janus Scott
• K Pattabhiraman
• Macpherson Mike
• Maiyuran Subramaniam
• Petre Marian Alin
• Ramadoss Murali
• Shah Shailesh
• Sinha Kamal
• Surti Prasoonkumar
• Vemulapalli Vikranth

Classifications

• G06F2212/652

  Page size control · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F2212/6026

  Prefetching based on access pattern detection, e.g. stride based prefetch · CPC title

• G06F2212/601

  Reconfiguration of cache memory · CPC title