Multi-tile graphics processor rendering

Patent metadata

Field	Value
Publication number	US-12094048-B2
Application number	US-202117497618-A
Country	US
Kind code	B2
Filing date	Oct 8, 2021
Priority date	Mar 15, 2019
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

First claim

What is claimed is:

1. An apparatus comprising:
a memory for storage of data, the data including geometric data for graphics processing; and
one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tile chiplets on a substrate, each of the plurality of GPU tile chiplets being a separate semiconductor chiplet;
wherein the apparatus is to:
assign geometric data to a plurality of screen tiles for rendering of graphics;
map each of the plurality of GPU tile chiplets to a respective screen tile of the plurality of screen tiles; and
perform tile-based rendering utilizing the plurality of GPU tile chiplets, wherein the tile-based rendering includes each GPU tile chiplet to render graphics utilizing the geometric data that is assigned to the screen tile that is mapped to the GPU tile chiplet.

2. The apparatus of claim 1 , wherein the tile-based rendering includes collecting, in a single render pass, all triangles that map to a screen tile of the plurality of screen tiles for processing at a GPU tile chiplet that is mapped to the screen tile.

3. The apparatus of claim 2 , wherein the collected triangles are sorted on a per screen tile basis among the plurality of screen tiles.

4. The apparatus of claim 2 , wherein pixel data relating to the collected triangles are mutually exclusive to a particular GPU tile chiplet on boundaries between the plurality of GPU tile chiplets.

5. The apparatus of claim 4 , wherein required attributes for pixel data of a GPU tile chiplet of the plurality of GPU tile chiplets are pushed from a geometry pipeline to the GPU tile chiplet.

6. One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
processing geometric data for graphics processing utilizing a graphics processing unit (GPU), wherein the GPU includes a plurality of GPU tile chiplets on a substrate, each of the plurality of GPU tile chiplets being a separate semiconductor chiplet;
assigning the geometric data to a plurality of screen tiles for rendering of graphics;
mapping each of the plurality of GPU tile chiplets to a respective screen tile of the plurality of screen tiles; and
performing tile-based rendering utilizing the plurality of GPU tile chiplets, wherein the tile-based rendering includes each GPU tile chiplet to render graphics utilizing the geometric data that is assigned to the screen tile that is mapped to the GPU tile chiplet.

7. The one or more computer-readable storage mediums of claim 6 , wherein the tile-based rendering includes collecting, in a single render pass, all triangles that map to a screen tile of the plurality of screen tiles for processing at a GPU tile chiplet that is mapped to the screen tile.

8. The one or more computer-readable storage mediums of claim 7 , further comprising instructions for sorting the collected triangles on a per screen tile basis among the plurality of screen tiles.

9. The one or more computer-readable storage mediums of claim 7 , wherein pixel data relating to the collected triangles are mutually exclusive to a particular GPU tile chiplet on boundaries between the plurality of GPU tile chiplets.

10. The one or more computer-readable storage mediums of claim 9 , further comprising instructions for pushing required attributes for pixel data of a GPU tile chiplet of the plurality of GPU tile chiplets from a geometry pipeline to the GPU tile chiplet.

11. A method comprising:
processing geometric data for graphics processing utilizing a graphics processing unit (GPU), wherein the GPU includes a plurality of GPU tile chiplets on a substrate, each of the plurality of GPU tile chiplets being a separate semiconductor chiplet;
assigning geometric data to a plurality of screen tiles for rendering of graphics;
mapping each of the plurality of GPU tile chiplets to a respective screen tile of the plurality of screen tiles; and
performing tile-based rendering utilizing the plurality of GPU tile chiplets, wherein the tile-based rendering includes each GPU tile chiplet to render graphics utilizing the geometric data that is assigned to the screen tile that is mapped to the GPU tile chiplet.

12. The method of claim 11 , wherein the tile-based rendering includes collecting, in a single render pass, all triangles that map to a screen tile of the plurality of screen tiles for processing at a GPU tile chiplet that is mapped to the screen tile.

13. The method of claim 12 , further comprising sorting the collected triangles on a per screen tile basis among the plurality of screen tiles.

14. The method of claim 12 , wherein pixel data relating to the collected triangles are mutually exclusive to a particular GPU tile chiplet on boundaries between the plurality of GPU tile chiplets.

15. The method of claim 14 , further comprising pushing required attributes for pixel data of a GPU tile chiplet of the plurality of GPU tile chiplets from a geometry pipeline to the GPU tile chiplet.

Assignees

• Intel Corp

Inventors

• Surti Prasoonkumar
• Hunter Arthur
• Sinha Kamal
• Janus Scott
• Insko Brent
• Ranganathan Vasanth
• Striramassarma Lakshminarayanan

Classifications

• G06T17/20

  Finite element generation, e.g. wire-frame surface description, {tesselation} · CPC title

• G06T1/60

  Memory management · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title