Apparatus and methods for testing devices
US-10989748-B2 · Apr 27, 2021 · US
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Gregory Paul E patents
Gregory Paul E is listed as an inventor on 19 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Gregory Paul E |
| Total patents | 19 |
| First publication | May 26, 2015 |
| Latest publication | Apr 27, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatus and methods for testing devices
US-2020348349-A1 · Nov 5, 2020 · US
Apparatus and methods for testing devices
US-10718805-B2 · Jul 21, 2020 · US
Advanced transistors with punch through suppression
US-10325986-B2 · Jun 18, 2019 · US
Semiconductor structure with multiple transistors having various threshold voltages
US-10217838-B2 · Feb 26, 2019 · US
Semiconductor Structure With Multiple Transistors Having Various Threshold Voltages and Method of Fabrication Thereto
US-2018261683-A1 · Sep 13, 2018 · US
Semiconductor structure with multiple transistors having various threshold voltages
US-10014387-B2 · Jul 3, 2018 · US
Apparatus and methods for testing devices
US-2017356946-A1 · Dec 14, 2017 · US
Semiconductor structure with multiple transistors having various threshold voltages
US-9812550-B2 · Nov 7, 2017 · US
Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages
US-2017141209-A1 · May 18, 2017 · US
Recent patents
Latest publications not already listed above.
Advanced Transistors with Punch Through Suppression
US-2017040419-A1 · Feb 9, 2017 · US
Advanced transistors with punch through suppression
US-9508800-B2 · Nov 29, 2016 · US
Advanced Transistors with Punch Through Suppression
US-2016181370-A1 · Jun 23, 2016 · US
Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages
US-2016163823-A1 · Jun 9, 2016 · US
Semiconductor structure with multiple transistors having various threshold voltages
US-9299698-B2 · Mar 29, 2016 · US
Advanced transistors with punch through suppression
US-9263523-B2 · Feb 16, 2016 · US
Semiconductor structure with improved channel stack and method for fabrication thereof
US-9111785-B2 · Aug 18, 2015 · US
Analog transistor
US-9093469-B2 · Jul 28, 2015 · US
Deeply depleted MOS transistors having a screening layer and methods thereof
US-9041126-B2 · May 26, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Mie Fujitsu Semiconductor Ltd | 15 |
| Micron Technology Inc | 4 |
| Suvolta Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/601 | 14 |
| H10D84/038 | 14 |
| H10D62/371 | 13 |
| H10D84/0128 | 13 |
| H10D30/0217 | 12 |