Semiconductor structure with multiple transistors having various threshold voltages

Patent metadata

Field	Value
Publication number	US-9812550-B2
Application number	US-201715419315-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Jun 27, 2012
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

First claim

What is claimed is:

1. A method of fabricating a semiconductor structure, comprising:
implanting in a substrate a first antipunchthrough region with a first doping concentration;
implanting in the substrate a second antipunchthrough region with a second doping concentration;
implanting in the substrate a screening region with a third doping concentration;
forming a substantially undoped channel on the substrate;
forming a gate on the substrate;
implanting in the substrate a source and a drain;
wherein the screening region is located to be below a surface of the substrate at a distance of at least less than 1.5 times a length of the gate and above a bottom of the source and drain to which the screening region abuts;
wherein the first antipunchthrough region underlies the screening region and the first doping concentration is less than the third doping concentration;
wherein the second antipunchthrough region underlies the first antipunchthrough region and the second doping concentration is less than the third doping concentration.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Zhao Dalong
• Bakhishev Teymur
• Scudder Lance
• Gregory Paul E
• Duane Michael
• Sridharan U C
• Ranade Pushkar
• Shifren Lucian
• Hoffmann Thomas

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L21/265

  Electricity · mapped topic

• H01L21/823412

  Electricity · mapped topic

• H01L21/283

  Electricity · mapped topic