Semiconductor structure with multiple transistors having various threshold voltages

Patent metadata

Field	Value
Publication number	US-10014387-B2
Application number	US-201615047052-A
Country	US
Kind code	B2
Filing date	Feb 18, 2016
Priority date	Jun 27, 2012
Publication date	Jul 3, 2018
Grant date	Jul 3, 2018

Abstract

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

First claim

What is claimed is:

1. A method of fabricating a semiconductor structure, comprising:
concurrently implanting in a substrate a first screening region for each of first, second, and third transistor elements;
implanting in the substrate a second screening region above the first screening region for the second transistor element;
implanting in the substrate a third screening region above the first screening region for the third transistor element;
forming a substantially undoped epitaxial layer covering the first, second, and third screening regions to form a channel layer for each of first, second, and third transistor elements,
wherein the first screening region is in contact with at least one of the second and third screening regions.

2. The method of claim 1 , wherein the first screening region is separated from at least one of the second and third screening regions.

3. The method of claim 1 , wherein a dopant concentration of the first screening region is higher than each of a dopant concentration of the second screening region and a dopant concentration of the third screening region different from the dopant concentration of the second screening region.

4. The method of claim 1 , wherein the third screening region is implanted at a lesser depth than the second screening region.

5. The method of claim 1 , wherein:
the channel layer on the substrate for each of the first, second, and third transistor elements is formed by a blanket epitaxial growth.

6. The method of claim 1 , further comprising:
concurrently implanting a first antipunchthrough region for each of the first, second, and third transistor elements;
concurrently implanting a second antipunchthrough region above the first antipunchthrough region for each of the first, second, and third transistor elements;
wherein the first and second antipunchthrough regions underlie the respective screening regions of the first, second, and third transistor elements.

7. The method of claim 6 , wherein the first antipunchthrough region is formed in contact with the second antipunchthrough region.

8. The method of claim 6 , wherein the second antipunchthrough region is formed in contact with the first screening region.

9. The method of claim 1 , wherein each of the transistor elements has a gate with a source and a drain on either side of the gate, each of the first and second screening regions extends laterally across the length of the channel and abuts the source and drain.

10. The method of claim 9 , wherein each of the first and second screening regions is located to be below the surface of the substrate at a distance of at least less than 1/1.5 times a length of the gate and above the bottom of the source and drain to which each of the screening regions abuts.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Zhao Dalong
• Bakhishev Teymur
• Scudder Lance
• Gregory Paul E
• Duane Michael
• Sridharan U C
• Ranade Pushkar
• Shifren Lucian
• Hoffmann Thomas

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L21/823412

  Electricity · mapped topic

• H01L29/1083

  Electricity · mapped topic

• H01L29/66477

  Electricity · mapped topic