Semiconductor structure with multiple transistors having various threshold voltages

Patent metadata

Field	Value
Publication number	US-10217838-B2
Application number	US-201815963598-A
Country	US
Kind code	B2
Filing date	Apr 26, 2018
Priority date	Jun 27, 2012
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

First claim

What is claimed is:

1. A method of fabricating a semiconductor structure, comprising:
implanting in a substrate a first antipunchthrough region for a transistor element;
implanting in the substrate a second antipunchthrough region for the transistor element;
implanting in the substrate a first screening region for the transistor element with a first dopant species;
implanting in the substrate a second screening region for the transistor element with a second dopant species different from the first dopant species;
forming a substantially undoped epitaxial layer covering the first and the second screening regions to form a channel layer for the transistor element, and
wherein the first dopant species and the second dopant species are of same polarity;

the second anitpunchthrough region is located under the first screening region and the second screening region, the first antipunchthrough region is located under the second antipunchthrough region.

2. The method of claim 1 , wherein the second dopant species is a heavier molecule than the first dopant species.

3. The method of claim 1 , wherein the first dopant species diffuses more than the second dopant species.

4. The method of claim 1 , wherein the first screening region at least partially overlaps with the second screening region in the depth direction.

5. The method of claim 1 , wherein the second screening region is shallower than the first screening region.

6. The method of claim 1 , wherein the first dopant species is B, the second dopant species is BF2 for an NMOS transistor.

7. The method of claim 1 , wherein the first dopant species is As, the second dopant species is Sb for an PMOS transistor.

8. The method of claim 1 , wherein the second antipunchthrough region at least partially overlaps with the first screening region in the depth direction.

9. The method of claim 1 , wherein the first antipunchthrough region at least partially overlaps with the second antipunchthrough region in the depth direction.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Zhao Dalong
• Bakhishev Teymur
• Scudder Lance
• Gregory Paul E
• Duane Michael
• Sridharan U C
• Ranade Pushkar
• Shifren Lucian
• Hoffmann Thomas

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L21/283

  Electricity · mapped topic

• H01L29/66477

  Electricity · mapped topic

• H01L29/105

  Electricity · mapped topic