Real-time error debugging
US-11669381-B1 · Jun 6, 2023 · US
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Gollub Marc A patents
Gollub Marc A is listed as an inventor on 61 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Gollub Marc A |
| Total patents | 61 |
| First publication | Mar 24, 2015 |
| Latest publication | Jun 6, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Real-time error debugging
US-2023153190-A1 · May 18, 2023 · US
Tracking address ranges for computer memory errors
US-11017875-B2 · May 25, 2021 · US
Performing error correction in computer memory
US-10971246-B2 · Apr 6, 2021 · US
Common high and low random bit error correction logic
US-10901839-B2 · Jan 26, 2021 · US
Common high and low random bit error correction logic
US-10824504-B2 · Nov 3, 2020 · US
Autonomous dram scrub and error counting
US-10628248-B2 · Apr 21, 2020 · US
Memory mirror invocation upon detecting a correctable error
US-10613951-B2 · Apr 7, 2020 · US
Common high and low random bit error correction logic
US-2020097359-A1 · Mar 26, 2020 · US
Auto-disabling DRAM error checking on threshold
US-10592332-B2 · Mar 17, 2020 · US
Recent patents
Latest publications not already listed above.
Selective error coding
US-10545824-B2 · Jan 28, 2020 · US
Common high and low random bit error correction logic
US-2019317856-A1 · Oct 17, 2019 · US
Performing error correction in computer memory
US-2019244676-A1 · Aug 8, 2019 · US
Tracking address ranges for computer memory errors
US-2019221280-A1 · Jul 18, 2019 · US
Managing entries in a mark table of computer memory errors
US-10353669-B2 · Jul 16, 2019 · US
Confirming memory marks indicating an error in computer memory
US-10338999-B2 · Jul 2, 2019 · US
Performing error correction in computer memory
US-10304560-B2 · May 28, 2019 · US
Tracking address ranges for computer memory errors
US-10297335-B2 · May 21, 2019 · US
Determining timeout values for computing systems
US-10268615-B2 · Apr 23, 2019 · US
Memory mirror invocation upon detecting a correctable error
US-2019079840-A1 · Mar 14, 2019 · US
Memory scrubbing in a mirrored memory system to reduce system power consumption
US-10228999-B2 · Mar 12, 2019 · US
Memory scrubbing in a mirrored memory system to reduce system power consumption
US-10223200-B2 · Mar 5, 2019 · US
Determining timeout values for computing systems
US-2019065421-A1 · Feb 28, 2019 · US
Memory system power management
US-10168936-B2 · Jan 1, 2019 · US
Memory error recovery
US-10140186-B2 · Nov 27, 2018 · US
Auto-disabling dram error checking on threshold
US-2018246781-A1 · Aug 30, 2018 · US
Efficient scrubbing of mirrored memory
US-2018232163-A1 · Aug 16, 2018 · US
Efficient scrubbing of mirrored memory
US-10048880-B1 · Aug 14, 2018 · US
Efficient scrubbing of mirrored memory
US-10007456-B1 · Jun 26, 2018 · US
Auto-disabling DRAM error checking on threshold
US-9996414-B2 · Jun 12, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 61 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0619 | 32 |
| G06F11/106 | 31 |
| G11C29/52 | 22 |
| G06F11/1068 | 21 |
| G06F3/064 | 21 |