Auto-disabling dram error checking on threshold

Patent metadata

Field	Value
Publication number	US-2018246781-A1
Application number	US-201815967609-A
Country	US
Kind code	A1
Filing date	May 1, 2018
Priority date	Jul 12, 2016
Publication date	Aug 30, 2018
Grant date	—

Abstract

An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects and error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

First claim

1 . A method of disabling error checking in a dynamic random access memory (DRAM), the method comprising:
receiving data at a DRAM; executing, at the DRAM, error checking logic based on the data; detecting, by the error checking logic, an error condition in the data; determining, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached; and disabling the error checking logic at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

2 . The method of claim 1 , wherein the disabling is performed by the DRAM.

3 . The method of claim 1 , wherein the error condition is a parity error and the data includes command or address data.

4 . The method of claim 1 , wherein the error condition is a cyclical redundancy check (CRC) error and the data includes write data.

5 . The method of claim 1 , wherein the DRAM is a double data rate fourth-generation synchronous DRAM (DDR4).

6 . The method of claim 1 , wherein the error threshold is determined to be reached based on a number of the error conditions previously detected exceeding a threshold count.

7 . The method of claim 1 , further comprising:
communicating the error condition to a memory controller in response to determining that detecting the error condition did not cause the error threshold to be reached, wherein the communicating is via an alert signal.

8 . The method of claim 7 , wherein the method further comprises, in response to the communicating, receiving the data at the DRM from the memory controller.

9 . A memory system comprising:
a memory device, the memory device including a dynamic random access memory (DRAM) configured for: receiving data at the DRAM; executing, at the DRAM, error checking logic based on the data; detecting, by the error checking logic, an error condition in the data; determining, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached; and disabling the error checking logic at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

10 . The system of claim 9 , wherein the error condition is a parity error and the data includes command or address data.

11 . The system of claim 9 , wherein the error condition is a cyclical redundancy check (CRC) error and the data includes write data.

12 . The system of claim 9 , wherein the DRAM is a double data rate fourth-generation synchronous DRAM (DDR4).

13 . The system of claim 9 , wherein the error threshold is determined to be reached based on a number of the error conditions previously detected exceeding a threshold count.

14 . The system of claim 9 , wherein the DRAM is further configured for communicating the error condition to a memory controller in response to determining that detecting the error condition did not cause the error threshold to be reached, wherein the communicating is via an alert signal.

15 . The system of claim 14 , wherein the DRAM is further configured for, in response to the communicating, receiving the data at the DRM from the memory controller.

16 . A computer program product for disabling error checking in a dynamic random access memory (DRAM), the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing circuitry to cause the processing circuitry to:
receive data at the DRAM; execute, at the DRAM, error checking logic based on the data; detect, by the error checking logic, an error condition in the data; determine, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached; and disable the error checking logic at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.

17 . The computer program product of claim 16 , wherein the error condition is a parity error and the data includes command or address data.

18 . The computer program product of claim 16 , wherein the error condition is a cyclical redundancy check (CRC) error and the data includes write data.

19 . The computer program product of claim 16 , wherein the DRAM is a double data rate fourth-generation synchronous DRAM (DDR4).

20 . The computer program product of claim 16 , wherein the error threshold is determined to be reached based on a number of the error conditions previously detected exceeding a threshold count.

Assignees

• IBM

Inventors

• Cordero Edgar R
• Gollub Marc A
• Maule Warren E
• Mulkey Lucas W
• Saetow Anuwat

Classifications

• G06F11/1052

  Bypassing or disabling error detection or correction · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title