Memory scrubbing in a mirrored memory system to reduce system power consumption

Patent metadata

Field	Value
Publication number	US-10223200-B2
Application number	US-201715810287-A
Country	US
Kind code	B2
Filing date	Nov 13, 2017
Priority date	Jul 30, 2015
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

First claim

What is claimed is:

1. A method to reduce power consumption of a fully mirrored memory subsystem comprising:
defining, with a processor, a scrub address range of a first memory portion of a fully mirrored memory module and defining a mirrored address range of a second memory portion of the fully mirrored memory module that is redundantly mirrored to the first memory portion, wherein the fully mirrored memory module consists of the first memory portion and the second memory portion;
reading, with the processor, data that is stored in the first memory portion and data that is stored in the second memory portion;
scrubbing, with the processor, first data read from the first portion at a reference scrub rate;
scrubbing, with the processor, second data mirroring the first data read from the second portion at a reduced scrub rate that is adjusted to be constantly less than the reference scrub rate;
monitoring, with the processor, a soft error rate of first data read from the first portion and scrubbed; and
adjusting, with the processor, the reference scrub rate and the reduced scrub rate based upon the monitored soft error rate of first data scrubbed from the first portion.

2. The method of claim 1 , wherein the reduced scrub rate is increased if the rate of soft errors detected within the first data read from the first memory portion exceeds a predetermined maximum threshold.

3. The method of claim 1 , wherein the reduced scrub rate is decreased if the rate of soft errors detected within the first data read from the first memory portion is less than a predetermined minimum threshold.

4. The method of claim 1 , wherein the first memory portion comprises a plurality of memory locations that are collectively identified by the scrub address range such that each scrub address within the scrub address range identifies a respective first memory portion memory location, wherein the second memory portion comprises a plurality of memory locations that are collectively identified by the mirrored address range such that each mirrored address within the mirrored address rage identifies a respective second memory portion memory location.

5. The method of claim 1 , wherein corrected first data is copied from the first memory portion to a mirrored memory location within the second memory portion if the processor identifies an uncorrectable error within second data read from the mirrored memory location within the second memory portion.

6. The method of claim 1 , wherein reading at the reduced scrub rate reduces the data that the processor reads from the second memory portion and scrubs.

7. The method of claim 6 , wherein power consumed by the fully mirrored memory subsystem is reduced by the processor reading at the reduced scrub rate from the second memory portion.

8. A fully mirrored memory subsystem comprising:
a fully mirrored memory module that stores data, the fully mirrored memory module consisting of a first memory portion and a second memory portion redundantly mirrored to the first memory portion;
a processor that reads data stored in the fully mirrored memory module, wherein the processor defines a scrub address range of the first memory portion and defines a mirrored address range of the second memory portion, the processor comprising:
a memory scrubbing circuit that scrubs data read from the first memory portion at a reference scrub rate and scrubs data read from the second memory portion at a reduced scrub rate that is adjusted to be constantly less than the reference scrub rate; and
a soft error rate monitor circuit that detects the rate of soft errors within the data read from the fully mirrored memory module corrected by the memory scrubbing circuit;
wherein the reduced scrub rate is adjusted to be constantly less than the reference scrub rate based upon the rate of soft errors detected within the data read from the first memory portion.

9. The fully mirrored memory subsystem of claim 8 , wherein the reduced scrub rate is increased if the rate of soft errors detected within the data read from the first memory portion exceeds a predetermined maximum threshold.

10. The fully mirrored memory subsystem of claim 8 , wherein the reduced scrub rate is decreased if the rate of soft errors detected within the data read from the first memory portion is less than a predetermined minimum threshold.

11. The fully mirrored memory subsystem of claim 8 , wherein the first memory portion comprises a plurality of memory locations that are collectively identified by the scrub address range such that each scrub address within the scrub address range identifies a respective first memory portion memory location, wherein the second memory portion comprises a plurality of memory locations that are collectively identified by the mirrored address range such that each mirrored address within the mirrored address rage identifies a respective second memory portion memory location.

12. The fully mirrored memory subsystem of claim 8 , wherein corrected data is copied from the first memory portion to a mirrored memory location within the second memory portion if the processor identifies an uncorrectable error within corresponding data read from the mirrored memory location within the second memory portion.

13. The fully mirrored memory subsystem of claim 8 , wherein reading at the reduced scrub rate reduces the data that the processor reads from the second memory portion and scrubs.

14. The fully mirrored memory subsystem of claim 8 , wherein power consumed by the fully mirrored memory subsystem is reduced by the processor reading at the reduced scrub rate from the second memory portion.

15. A computer comprising:
a fully mirrored memory module that stores data, the fully mirrored memory module consisting of a first memory portion and a second memory portion redundantly mirrored to the first memory portion;
a processor that reads data stored in the fully mirrored memory module, wherein the processor defines a scrub address range of the first memory portion and defines a mirrored address range of the second memory portion, the processor comprising:
a memory scrubbing circuit that scrubs data read from the first memory portion at a reference scrub rate and scrubs data read from the second memory portion at a reduced scrub rate that is adjusted to be constantly less than the reference scrub rate; and
a soft error rate monitor circuit that detects the rate of soft errors within the data read from the memory corrected by the memory scrubbing circuit;
wherein the reduced scrub rate is adjusted to be constantly less than the reference scrub rate based upon the rate of soft errors detected within the data read from the first memory portion.

16. The computer of claim 15 , wherein the reduced scrub rate is increased if the rate of soft errors detected within the data read from the first memory portion exceeds a predetermined maximum threshold.

17. The computer of claim 15 , wherein the reduced scrub rate is decreased if the rate of soft errors detected within the data read from the first memory portion is less than a predetermined minimum threshold.

18. The computer of claim 15 , wherein the first memory portion comprises a plurality of memory locations that are collectively identified by the scrub address range such that each scrub address within the scrub address range identifies a respective first memory portion memory location, wherein the second memory portion comprises a plurality of memory locations that are collectively identified by the mirrored address range such that each mirrored addre

Assignees

• IBM

Inventors

• Chinnakkonda Vidyapoornachary Diyanesh B
• Gollub Marc A
• Sawan Tony E

Classifications

• G11C2029/0409

  Online test · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0673

  Single storage device · CPC title