Translation cache and configurable ECC memory for reducing ECC memory overhead
US-12572417-B2 · Mar 10, 2026 · US
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Galbi Duane E patents
Galbi Duane E is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Galbi Duane E |
| Total patents | 21 |
| First publication | Apr 23, 2020 |
| Latest publication | Mar 10, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Remote storage for hardware microservices hosted on XPUs and SOC-XPU platforms
US-12450008-B2 · Oct 21, 2025 · US
Cache management in a multi-processor system
US-2025252055-A1 · Aug 7, 2025 · US
Data pre-fetch for large language model (llm) processing
US-2024370699-A1 · Nov 7, 2024 · US
Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs
US-12111775-B2 · Oct 8, 2024 · US
Memory striping approach that interleaves sub protected data words
US-12099408-B2 · Sep 24, 2024 · US
Input/output (i/o) virtualization acceleration
US-2023333921-A1 · Oct 19, 2023 · US
Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth
US-11699471-B2 · Jul 11, 2023 · US
Cross dram dimm sub-channel pairing
US-2023215493-A1 · Jul 6, 2023 · US
Technologies for hardware microservices accelerated in xpu
US-2023185760-A1 · Jun 15, 2023 · US
Recent patents
Latest publications not already listed above.
Method and apparatus to store and process telemetry data in a network device in a data center
US-2022321434-A1 · Oct 6, 2022 · US
Microservice data path and control path processing
US-2022321491-A1 · Oct 6, 2022 · US
Workload execution based on device characteristics
US-2022206864-A1 · Jun 30, 2022 · US
Remote storage for hardware microservices hosted on xpus and soc-xpu platforms
US-2022113911-A1 · Apr 14, 2022 · US
Flexible configuration of memory module data width
US-2022012173-A1 · Jan 13, 2022 · US
Enabling logic for flexible configuration of memory module data width
US-2022012195-A1 · Jan 13, 2022 · US
Translation cache and configurable ecc memory for reducing ecc memory overhead
US-2022012126-A1 · Jan 13, 2022 · US
Memory accesses using a memory hub
US-2021209035-A1 · Jul 8, 2021 · US
Memory striping approach that interleaves sub protected data words
US-2021191811-A1 · Jun 24, 2021 · US
Synchronous dynamic random access memory (sdram) dual in-line memory module (dimm) having increased per data pin bandwidth
US-2021005234-A1 · Jan 7, 2021 · US
Multi-level memory with improved memory side cache implementation
US-2020125495-A1 · Apr 23, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 21 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2209/509 | 4 |
| G11C11/4093 | 4 |
| G11C5/04 | 4 |
| G11C11/4076 | 4 |
| G06F2212/1016 | 4 |