Translation cache and configurable ecc memory for reducing ecc memory overhead

Patent metadata

Field	Value
Publication number	US-2022012126-A1
Application number	US-202117483536-A
Country	US
Kind code	A1
Filing date	Sep 23, 2021
Priority date	Sep 23, 2021
Publication date	Jan 13, 2022
Grant date	—

Abstract

A translation cache and configurable error checking and correction (“ECC”) memory reduces ECC memory overhead. The translation cache supports a configurable ECC memory capable of storing a portion of a cache line, along with any ECC data, in corresponding parts of memory devices to reduce the ECC memory overhead in a memory subsystem. The corresponding parts include any same one of an upper, lower, left or right part of memory devices in a memory module, including dynamic random access memory (“DRAM”) devices in a dual inline memory module (“DIMM”).

First claim

What is claimed is:

1 . A system comprising:
a processor; a translation cache between the processor and a memory subsystem; and the processor to manage the translation cache including to:
receive one or more portions of cached data in the translation cache, the cached data including an error checking and correction (“ECC”) data to correct each of the one or more portions of the cached data;
determine that the one or more portions of the cached data exceed an internal processor cache width; and
process the one or more portions of the cached data to reduce overhead for storing the ECC data in the memory subsystem.

2 . The system of claim 1 , wherein:
to process the one or more portions of the cached data to reduce overhead for storing the ECC data in the memory subsystem, the processor is further to:
use any of a burst length or corresponding parts of memory devices to access the cached data to determine which portion of the cached data in the translation cache to process; and
hold any one or more remaining portions of the cached data in the translation cache to allow the processor to any of write and read all remaining portions before the translation cache is flushed.

3 . The system of claim 1 , wherein:
the memory subsystem includes memory devices capable of storing the one or more portions of the cached data, including the ECC data, in corresponding parts of the memory devices to reduce overhead for storing the ECC data in the memory subsystem; the corresponding parts includes any same one of an upper, lower, left and right parts of the memory devices, the corresponding parts capable of storing any of the one or more portions of the cached data, including storing the ECC data in a corresponding part of a separate memory device; and wherein to process the one or more portions of the cached data to reduce overhead for storing the ECC data in the memory subsystem, the processor is to read from and write to the memory devices capable of storing the one or more portions of the cached data in the corresponding parts of the memory devices, including the ECC data.

4 . The system of claim 3 , wherein the memory devices include dynamic random access memory (“DRAM”) devices, and further wherein any of:
the DRAM devices include any of an x4 and an x8 DRAM device operating in accordance with a double data rate (“DDR”) standard, including DDR version 5;
the DRAM devices are included in a dual inline memory module (“DIMM”) compliant with full single device data correction (“SDDC”), the DIMM including a failure domain of one DRAM device in the DRAM devices comprising the DIMM; and
the DRAM devices support bounded failure (“BF”) in which each part of the DRAM devices, including both halves of the DRAM devices, operate as independent failure domains.

5 . The system of claim 3 , wherein the processor is further to determine a mode of operation of the processor based on the memory subsystem, including to determine any of:
a memory cache width of the memory subsystem is larger than an internal cache width of the processor; a state of a register in the memory subsystem controlling the mode of operation of the processor; and wherein the mode of operation of the processor controls how the processor manages the translation cache.

6 . The system of claim 5 , wherein the memory cache width is any multiple of the internal cache width of the processor, including a width of 128 bytes, a multiple of the internal cache width of the processor of 64 bytes.

7 . The system of claim 5 , wherein the translation cache is a memory side cache (“MSC”) having a full cache width, the full cache width matching the memory cache width of the memory subsystem.

8 . The system of claim 5 , wherein the translation cache is a redefined last level cache of the processor, including a redefined level three (L3) cache, the redefined last level cache having a cache width matching the internal cache width of the processor, the system further comprising:
an interface to the memory subsystem, the interface having a larger cache width than the internal cache width of the processor; a write order buffer coupled to the redefined last level cache and the interface to the memory subsystem, the write order buffer having a width matching the internal cache width of the processor; and a read hold buffer coupled to the redefined last level cache and the interface to the memory subsystem, the read hold buffer having a width matching the internal cache width of the processor.

9 . The system of claim 8 , wherein:
to process one or more portions of the cached data to reduce overhead for storing the ECC data in the memory subsystem, the processor further to: read from the read hold buffer all of a read data read from the memory subsystem via the interface, and write to the write order buffer all of a write data written to the memory subsystem via the interface; and further wherein the processor to manage eviction processes in the redefined last level cache, including to: cache any level two (L2) dirty evicts in the redefined last level cache, pair evictions in the redefined last level cache, including cleaning determined portions of the cache along with any remaining portion of the cache associated with the determined portion, flush any unpaired writes from the write order buffer during any one or more free memory cycles of the processor, and hold any unused portion of read data received in the redefined last level cache via the interface to the memory subsystem in the read hold buffer.

10 . The system of claim 8 , wherein the larger cache width of the interface is any multiple of the internal cache width of the processor, including 128 bytes, a multiple of the internal cache width of the processor of 64 bytes.

11 . An apparatus comprising:
a circuitry coupled to a memory subsystem having a memory cache line width, the circuitry to:
translate cached data with the memory cache line width into a translation cache of one or more cache sub-lines matching an internal processor cache line width, each cache sub-line including an error checking and correction (“ECC”) data to error check and correct the cached data in the cache sub-line,
hold any of the one or more cache sub-lines in the translation cache to allow sufficient time to any of write and read all cache sub-lines for the cached data before the translation cache is flushed; and
wherein the cache sub-lines, including the ECC data, are stored in corresponding parts of memory devices of the memory subsystem to reduce memory device overhead to store ECC data.

12 . The apparatus of claim 11 , the circuitry further to determine the one or more cache sub-lines based on any of:
a burst length, wherein a first half of the burst length corresponds to a first cache sub-line and a second half of the burst length corresponds to a second cache sub-line; and the corresponding parts of the memory devices in which the cache sub-lines are stored, wherein a first set of parts corresponds to the first cache sub-line and a second set of parts corresponds to the second cache sub-line.

13 . The apparatus of claim 11 , wherein:
the corresponding parts of the memory devices in which the cache sub-lines are stored include any same one of an upper, lower, right and left parts of the memory devices, including storing the ECC data for a cache sub-line in any of a corresponding part of a separate memory device separate from memory devices in which data for the cache sub-line is stored; and the circuitry further to read from and write to the corresponding parts of the memory devices in which the cache sub-lines are stored.

Assignees

• Intel Corp

Inventors

• Galbi Duane E
• Heirman Wim
• Ziakas Dimitrios

Classifications

• G06F11/1064

  in cache or content addressable memories · CPC title

• G06F2212/403

  Error protection encoding, e.g. using parity or ECC codes · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title