Memory striping approach that interleaves sub protected data words

Patent metadata

Field	Value
Publication number	US-12099408-B2
Application number	US-202017132982-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.

First claim

The invention claimed is:

1. An apparatus, comprising:
a memory controller comprising logic circuitry to write a unit of write data into a plurality of memory chips of a memory channel according to a striping pattern that comprises multiple protected sub words, each protected sub word comprising a smaller portion of the unit of write data and error correction code (ECC) information calculated from the smaller portion of the unit of write data, wherein, the memory controller is to implement the striping pattern in response to a failure of a memory chip of the memory channel, and wherein, the striping pattern causes a ratio of ECC information to write data to increase after the failure of the memory chip and causes the memory channel's utilized number of memory chips to decrease after the failure of the memory chip.

2. The apparatus of claim 1 wherein the striping pattern further comprises first information of more than one of the protected sub words during a full burst, and, second information of the more than one of the protected sub words during a partial burst.

3. The apparatus of claim 1 wherein the logic circuitry is further to:
process the respective data and error correction coding (ECC) of the multiple protected sub words independently; and,
if the respective data is valid, combine the respective data of the multiple protected sub words to form a unit of read data.

4. The apparatus of claim 1 wherein the striping pattern forms two protected sub words, where, the two protected sub words have different halves of the unit of write data.

5. The apparatus of claim 1 wherein the unit of write data is 64 bytes.

6. The apparatus of claim 1 wherein the unit of write data is 128 bytes.

7. The apparatus of claim 1 wherein data and error correction coding (ECC) from a same protected sub word are not stored in a same failure region of a same one of the plurality of memory chips.

8. The apparatus of claim 1 wherein at least one of the plurality of memory chips stores data and error correction coding (ECC) for different ones of the protected sub words.

9. A computing system, comprising:
a processor;
memory that the processor is to access; and,
a memory controller coupled between the processor and the memory, the memory controller comprising logic circuitry to write a unit of write data into a plurality of memory chips, of a memory channel of the memory according to a striping pattern that comprises multiple protected sub words, each protected sub word comprising a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data, wherein, the memory controller is to implement the striping pattern in response to a failure of a memory chip of the memory channel, and wherein, the striping pattern causes a ratio of ECC information to write data to increase after the failure of the memory chip and causes the memory channel's utilized number of memory chips to decrease after the failure of the memory chip.

10. The computing system of claim 9 wherein the striping pattern further comprises first information of more than one of the protected sub words during a full burst, and, second information of the more than one of the protected sub words during a half burst.

11. The computing system of claim 9 wherein the logic circuitry is further to:
process the respective data and error correction coding (ECC) of the multiple protected sub words independently; and,
if the respective data is valid, combine the respective data of the multiple protected sub words to form a unit of read data.

12. The computing system of claim 9 wherein the striping pattern forms two protected sub words, where, the two protected sub words have different halves of the unit of write data.

13. The computing system of claim 9 wherein the plurality of memory chips are on a memory module that allows less than all the memory chips of a rank to be accessed.

14. A method, comprising:
in response to a memory chip failure of a memory channel, applying a new write striping pattern to a plurality of memory chips of the memory channel, wherein, the new write striping pattern comprises multiple protected sub words, each protected sub word comprising a smaller portion of a unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data, wherein, the new write striping pattern causes a ratio of ECC information to write data to increase after the memory chip failure and causes the memory channel's utilized number of memory chips to decrease after the memory chip failure.

Assignees

• Intel Corp

Inventors

• Galbi Duane E
• Adiletta Matthew J

Classifications

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F12/0879

  Burst mode · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title