Flexible configuration of memory module data width

Patent metadata

Field	Value
Publication number	US-2022012173-A1
Application number	US-202117484418-A
Country	US
Kind code	A1
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Jan 13, 2022
Grant date	—

Abstract

A memory system has a configurable mapping of address space of a memory array to address of a memory access command. In response to a memory access command, a memory device can apply a traditional mapping of the command address to the address space, or can apply an address remapping to remap the command address to different address space.

First claim

What is claimed is:

1 . A memory device, comprising:
a configuration register to store one or more bits to indicate an address mapping for a memory array of the memory device, wherein the address mapping is to indicate a remapping of addresses of the memory array to an address higher than a maximum address range of the memory array; input/output (I/O) hardware to receive a memory access command with an address; and control circuitry to access a portion of the memory array in response to the memory access command, the portion of the memory array selected based on the remapping of addresses for the memory array.

2 . The memory device of claim 1 , wherein the remapping of the addresses of the memory array comprises a remapping of row addresses.

3 . The memory device of claim 1 , wherein the control circuitry is to access the portion of the memory array selected based on the remapping of the addresses of the memory array and an indication to apply the remapping of addresses.

4 . The memory device of claim 3 , wherein the indication comprises a command encoding.

5 . The memory device of claim 4 , wherein the command encoding comprises a command encoding of an activate command.

6 . The memory device of claim 4 , wherein the command encoding comprises a command encoding of a read command or a write command.

7 . The memory device of claim 3 , wherein the indication comprises the address of the memory access command.

8 . The memory device of claim 1 , wherein the configuration register is to store a fixed configuration to indicate the remapping of addresses of the memory array.

9 . The memory device of claim 1 , wherein the configuration register is to store a value programmable by a mode register write command.

10 . The memory device of claim 1 , wherein the remapping of the addresses of the memory array is to indicate a remapping for row addresses higher than a maximum row address of the memory array.

11 . The memory device of claim 1 , wherein the memory device is one of multiple parallel memory devices, and wherein different parallel memory devices are to apply different remappings of addresses.

12 . The memory device of claim 1 , further comprising:
a hardware interface to a data bus, wherein the memory device is to self-enable the hardware interface to the data bus in response to the memory access command.

13 . A computer system, comprising:
multiple memory devices connected in parallel, the memory devices including respective configuration registers to store respective values to indicate an address mapping for memory arrays of the respective memory devices, wherein the address mapping is to indicate a remapping of addresses of the memory array to an address higher than a maximum address range of the memory array; memory controller including input/output (I/O) hardware to send a memory access command with an address to the memory devices, wherein the memory devices are to select a portion of the memory array to access in respective memory arrays based on the address and respective remappings of addresses for respective memory arrays.

14 . The computer system of claim 13 , wherein the remapping of the addresses of the respective memory arrays comprises remapping of row addresses of the respective memory arrays.

15 . The computer system of claim 13 , wherein the memory controller is to send an indication to apply the address remapping.

16 . The computer system of claim 15 , wherein the indication comprises a command encoding of an activate command, or a read command, or a write command.

17 . The computer system of claim 13 , further comprising:
a data bus coupled between the multiple memory devices and the memory controller; wherein the multiple memory devices are to self-enable respective hardware interfaces to the data bus in response to the memory access command.

18 . The computer system of claim 13 , wherein the multiple memory devices comprise memory devices of a dual inline memory module (DIMM), wherein different memory devices of the DIMM are to apply different address mappings.

19 . The computer system of claim 18 , wherein data memory devices of the DIMM are to directly map an address of the memory access command to the memory array, and metadata memory devices are to apply the address remapping.

20 . The computer system of claim 13 , wherein the multiple memory devices comprise memory devices of a multichip package with a stack of multiple memory devices, wherein different memory devices of the multichip package are to apply different address mappings.

21 . The computer system of claim 13 , wherein one or more of:
further comprising a multicore host processor coupled to the memory controller; the computer system includes a display communicatively coupled to a processor; the computer system includes a network interface communicatively coupled to a processor; or the computer system includes a battery to power the computer system.

22 . A method comprising:
receiving a memory access command from a memory controller at a memory device, the memory access command having an address; determining if the memory access command has an associated remapping indication; applying a of the address of the memory access command directly to an address of a memory array of the memory device when the memory access command does not have an associated remapping indication; and applying an address remapping for the memory array based on the address when the memory access command has an associated remapping indication.

23 . The method of claim 22 , wherein determining if the memory access command has the associated remapping indication comprises decoding a command encoding of the memory access command.

24 . The method of claim 22 , further comprising:
receiving a mode register write command to configure the address remapping.

Assignees

• Intel Corp

Inventors

• Galbi Duane E
• Bains Kuljit S

Classifications

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C2207/105

  Aspects related to pads, pins or terminals · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title