Cross dram dimm sub-channel pairing

Patent metadata

Field	Value
Publication number	US-2023215493-A1
Application number	US-202318120907-A
Country	US
Kind code	A1
Filing date	Mar 13, 2023
Priority date	Mar 13, 2023
Publication date	Jul 6, 2023
Grant date	—

Abstract

Methods and apparatus for Cross DRAM DIMM sub-channel pairing. Memory channels on a memory controller or System on a Chip (SoC) are segmented into two subchannels, each including Command and Address (C/A) signals, DQ (data) lines. Under different solutions the two subchannels may share a command-bus clock or use separate command-bus clocks. Some approaches use subchannels from different memory channels to provide the C/A and DQ lines for two subchannels to a given DIMM. One solution implements an additional command-bus clock on the DIMM connector repurposing existing MCR pins to provide command-bus clock signals to a Registered Clock Driver (RCD) to allow the subchannels to be fully independent. Another solution is the pair every other DRAM controller to the same command-bus clock. Other solutions employ Skip-1, Skip-2, and Skip-3 configurations under which the clocks for the DDR-IO circuitry are not logically co-located with the subchannel IO circuitry.

First claim

What is claimed is:

1 . A System on a Chip (SoC) comprising:
a plurality of memory channels having input-output (IO) interface circuitry comprising a plurality of signals, including,
a first subset of signals associated with a first subchannel including a first set of command and address (C/A) signals, and a first set of data lines;
a second subset of signals associated with a second subchannel including a second set of C/A signals, and a second set of data lines; and
and at least one clock signal to be used as a command-bus clock for at least one of the first and second sets of C/A signals.

2 . The SoC of claim 1 , wherein circuitry is laid out on an SoC die such that the IO interface circuitry for the memory channels includes clock circuitry that is proximate to the IO circuitry for the first and second subchannels, and wherein the clock circuitry for a first memory channel is configured to provide a command-bus clock signal for a Dynamic Random Access Memory (DRAM) Dual Inline Memory Module (DIMM) that is connected to at least one subchannel for a second memory channel.

3 . The SoC of claim 2 , wherein clocks for pairs of adjacent memory channel IO interfaces are swapped such that the clock circuitry for a first memory channel IO interface is used with the C/A signals for a second memory channel IO interface and the clock circuitry for the second memory channel IO is used with the C/A signals for the first memory channel IO interface.

4 . The SoC of claim 1 , wherein each memory channel includes associated clock circuitry and the IO circuitry for sequential memory channels occupy a vertical or horizontal edge of an SoC die, and wherein a skip 1 configuration is used under which clock circuitry associated with a first given memory channel is used to provide a command-bus clock signal for the C/A signals for a second given memory channel that is separated from the first given memory channel by one memory channel disposed therebetween.

5 . The SoC of claim 1 , wherein each memory channel includes associated clock circuitry and the IO circuitry for sequential memory channels occupy a vertical or horizontal edge of an SoC die, and wherein a skip 2 configuration is used under which clock circuitry associated with a first given memory channel is used to provide a command-bus clock signal for the C/A signals for a second given memory channel that is separated from the first given memory channel by two memory channels disposed therebetween.

6 . The SoC of claim 1 , wherein each memory channel includes associated clock circuitry and the IO circuitry for sequential memory channels occupy a vertical or horizontal edge of an SoC die, and wherein a skip 3 configuration is used under which clock circuitry associated with a first given memory channel is used to provide a command-bus clock signal for the C/A signals for a second given memory channel that is separated from the first given memory channel by three memory channels disposed therebetween.

7 . The SoC of claim 1 , wherein the SoC comprises one or more dies, and wherein the clock circuitry for a given die is configured such that the clock signals for at least two memory channels are synchronized.

8 . A system, comprising:
a printed circuit board (PCB) or substrate; a System on a Chip (SoC) mounted to the PCB or substrate comprising a plurality of memory channels having input-output (IO) interface circuitry comprising a plurality of signals, including,
a first subset of signals associated with a first subchannel including a first set of command and address (C/A) signals, and a first set of data lines;
a second subset of signals associated with a second subchannel including a second set of command and address (C/A) signals, and a second set of data lines; and
and at least one command-bus clock signal to be used with the first and second sets of C/A signals;
a plurality of Dynamic Random Access Memory (DRAM) Dual Inline Memory Modules (DIMMs) operative coupled to the PCB or substrate, each DRAM DIMM including interface circuitry to support two subchannels, each subchannel having a respective set of C/A signals and data lines, each DRAM DIMM further having at least one registered clock driver RCD) input, wherein the PCB or substrate includes wiring connecting the set of C/A signals and data lines associated with each subchannel to a respective subchannel interface on a DRAM DIMM.

9 . The system of claim 8 , wherein a DRAM DIMM includes first and second RCD inputs, each associated with C/A signals corresponding to a respective subchannel.

10 . The system of claim 9 , wherein clock circuitry associated with a first memory channel on the SoC is coupled to first RCD inputs for a pair of DRAM DIMMs, and wherein clock circuitry associated with a second memory channel on the SoC is coupled to second RCD inputs for the pair of DRAM DIMMs via wiring in the PCB or substrate.

11 . The system of claim 8 , wherein the SoC includes one or more dies, wherein circuitry is laid out on an SoC die such that each memory channel IO interface circuitry includes clock circuitry that is proximate to the IO circuitry for the first and second subchannels, and wherein the clock circuitry for a first memory channel is configured to provide a command-bus clock signal that is received at an RCD input for a DRAM DIMM that is connected to at least one subchannel for a second memory channel.

12 . The system of claim 11 , wherein clocks for pairs of adjacent memory channel IO interfaces are swapped on an SoC die such that the clock circuitry for a first memory channel IO is used with the C/A signals for a second memory channel IO and the clock circuitry for the second memory channel IO is used with the C/A signals for the first memory channel IO.

13 . The system of claim 8 , wherein the C/A signals and data signals for first and second subchannels associated with a set of memory channel are connected to IO interface circuitry for respective first and second subchannels on respective DRAM DIMMs.

14 . The system of claim 8 , wherein each memory channel includes associated clock circuitry and the IO circuitry for sequential memory channels occupy a vertical or horizontal edge of an SoC die, and wherein a skip 2 configuration is used under which clock circuitry associated with a first given memory channel is used to provide a command-bus clock signal for the C/A signals for a subchannel associated with a second given memory channel that is separated from the first given memory channel by two memory channels disposed therebetween.

15 . The system of claim 8 , wherein each memory channel includes associated clock circuitry and the IO circuitry for sequential memory channels occupy a vertical or horizontal edge of an SoC die, and wherein a skip 3 configuration is used under which clock circuitry associated with a first given memory channel is used to provide a command-bus clock signal for the C/A signals for a subchannel associated with second given memory channel that is separated from the first given memory channel by three memory channels disposed therebetween.

16 . A memory module comprising:
memory channel input-output (TO) interface circuitry configured to interface with (IO) circuitry for first and second memory subchannels, comprising at least one command-bus clock signal and respective first and second sets of signal lines for the first and second subchannels including Command/Address (C/A) signal lines and a DQ lines; at least one registered clock driver (RCD) component; and a plurality of Dynamic Random Access Memory (DRAM) devices, each comprising,
IO

Assignees

• Intel Corp

Inventors

• Galbi Duane E
• Adiletta Matthew J
• Rashid Mohammad M
• Hinck Todd
• Boddu Vijaya K

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4093 Primary

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title