Translation cache and configurable ECC memory for reducing ECC memory overhead

Patent metadata

Field	Value
Publication number	US-12572417-B2
Application number	US-202117483536-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Sep 23, 2021
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A translation cache and configurable error checking and correction (“ECC”) memory reduces ECC memory overhead. The translation cache supports a configurable ECC memory capable of storing a portion of a cache line, along with any ECC data, in corresponding parts of memory devices to reduce the ECC memory overhead in a memory subsystem. The corresponding parts include any same one of an upper, lower, left or right part of memory devices in a memory module, including dynamic random access memory (“DRAM”) devices in a dual inline memory module (“DIMM”).

First claim

What is claimed is:

1 . An apparatus comprising:
a circuitry coupled to a memory subsystem having a memory cache line width, the circuitry to:
translate cached data with the memory cache line width into a translation cache of one or more cache sub-lines matching an internal processor cache line width, each cache sub-line including an error checking and correction (ECC) data to error check and correct the cached data in the cache sub-line,
hold any of the one or more cache sub-lines in the translation cache to allow sufficient time to any of write and read all cache sub-lines for the cached data before the translation cache is flushed; and
wherein the cache sub-lines, including the ECC data, are stored in corresponding parts of memory devices of the memory subsystem to reduce memory device overhead to store ECC data.

2 . The apparatus of claim 1 , the circuitry further to determine the one or more cache sub-lines based on any of:
a burst length, wherein a first half of the burst length corresponds to a first cache sub-line and a second half of the burst length corresponds to a second cache sub-line; and the corresponding parts of the memory devices in which the cache sub-lines are stored, wherein a first set of parts corresponds to the first cache sub-line and a second set of parts corresponds to the second cache sub-line.

3 . The apparatus of claim 1 , wherein:
the corresponding parts of the memory devices in which the cache sub-lines are stored include any same one of an upper, lower, right and left parts of the memory devices, including storing the ECC data for a cache sub-line in any of a corresponding part of a separate memory device separate from memory devices in which data for the cache sub-line is stored; and the circuitry further to read from and write to the corresponding parts of the memory devices in which the cache sub-lines are stored.

4 . The apparatus of claim 1 , wherein the memory devices include dynamic random access memory (DRAM) devices, and further wherein any of:
the DRAM devices include any of an x4 and an x8 DRAM device operating in accordance with a double data rate (DDR) standard, including DDR version 5; the DRAM devices are included in a dual inline memory module (DIMM) compliant with full single device data correction (SDDC), the DIMM including a failure domain of one DRAM device in the DRAM devices comprising the DIMM; and the DRAM devices support bounded failure (BF) in which each part of the DRAM devices operate as independent failure domains.

5 . The apparatus of claim 1 , the circuitry further to perform a standard cache process when any of the memory cache line width is determined to match the internal processor cache line width and the memory subsystem is determined not capable of storing the cached data to reduce memory device overhead to store the ECC data.

6 . The apparatus of claim 1 , the circuitry further to determine a mode of operation including to determine any of:
a state of a register in the memory subsystem controlling the mode of operation; and wherein the mode of operation causes the circuitry to perform a standard cache process when the state of the register indicates the memory subsystem does not include memory devices capable of storing data, including the ECC data, in the corresponding parts of the memory devices to reduce overhead for storing the ECC data.

7 . The apparatus of claim 1 , wherein the memory cache width is any multiple of the internal processor cache line width, including a width of 128 bytes, a multiple of the processor internal cache line width of 64 bytes.

8 . The apparatus of claim 1 , wherein the translation cache is a memory side cache (MSC) having a full cache width, the full cache width matching the memory cache width of the memory subsystem.

9 . The apparatus of claim 1 wherein the translation cache is a redefined last level cache, including a redefined level three (L3) cache, the redefined last level cache having a cache width matching the processor internal cache line width, the apparatus further comprising:
an interface to the memory subsystem, the interface having a larger cache width than any of the processor internal cache line width and the memory cache width of the memory subsystem;
a write order buffer coupled to the redefined last level cache and the interface to the memory subsystem, the write order buffer having a width matching the processor internal cache line width; and
a read hold buffer coupled to the redefined last level cache and the interface to the memory subsystem, the read hold buffer having a width matching the processor internal cache line width.

10 . The apparatus of claim 9 , wherein the circuitry further to:
cache any level two (L2) dirty evicts in the redefined last level cache; pair evictions in the redefined last level cache, including cleaning cache sub-lines for the cached data; flush any unpaired writes from the write order buffer during any one or more free memory cycles; and hold any unused portion of read data received in the redefined last level cache via the interface to the memory subsystem in the read hold buffer.

11 . The apparatus of claim 9 , wherein the larger cache width of the interface is any multiple of the processor internal cache line width, including 128 bytes equal to a multiple of the processor internal cache line width of 64 bytes.

12 . A system comprising:
a processor; a memory subsystem of memory devices in which to store cached data, including an error checking and correction (ECC) data, the memory subsystem having a memory cache line width; a translation cache between the processor and the memory subsystem; and the processor to manage the translation cache including to: use any of a burst length or corresponding parts of the memory devices to access the cached data to determine which portion of the cached data to process in the translation cache, receive one or more portions of the cached data in the translation cache, the cached data including the ECC data to correct each of the one or more portions of the cached data, determine that the one or more portions of the cached data exceed an internal processor cache line width, and process the one or more portions of the cached data to reduce overhead to store the ECC data in the memory subsystem, including to: translate the one or more portions of the cached data into a translation cache of one or more cache sub-lines matching the internal processor cache line width, each cache sub-line including the ECC data to error check and correct the cached data in the cache sub-line, and hold any of the one or more cache sub-lines in the translation cache to allow sufficient time for the processor to any of write and read all cache sub-lines for the cached data before the translation cache is flushed.

13 . The system of claim 12 , wherein:
the corresponding parts of the memory devices includes any same one of an upper, lower, left and right parts of the memory devices, the corresponding parts to store any of the one or more portions of the cached data, including to store the ECC data in a corresponding part of a separate memory device; and to process the one or more portions of the cached data, the processor is to read from and write to the memory devices to store the one or more portions of the cached data, including the ECC data, in the corresponding parts of the memory devices.

14 . The system of claim 12 , wherein the processor is further to determine a mode of operation to control how the processor manages the translation cache, including to determine any of:
the memory cache line width o

Assignees

• Intel Corp

Inventors

• Galbi Duane E
• Heirman Wim
• Ziakas Dimitrios

Classifications

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/12

  Replacement control · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title

• G06F2212/403

  Error protection encoding, e.g. using parity or ECC codes · CPC title