Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs

Patent metadata

Field	Value
Publication number	US-12111775-B2
Application number	US-202117212722-A
Country	US
Kind code	B2
Filing date	Mar 25, 2021
Priority date	Dec 26, 2020
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub. In some examples, based on provision of the at least some but not all home agent operations to be performed by the second home agent, the second home agent is to perform the at least some but not all home agent operations.

First claim

What is claimed is:

1. An apparatus comprising:
at least two processing units comprising at least two processor sockets and
a memory hub coupled to the at least two processing units, the memory hub comprising a home agent, wherein:
the home agent of the memory hub is to maintain cache coherency among the at least two processing units,
the cache coherency among the at least two processing units comprises access a copy of modified content of a cache line,
the at least two processor sockets comprise at least two central processing units (CPUs),
the at least two CPUs comprise cores, and
to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub.

2. The apparatus of claim 1 , wherein:
the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub.

3. The apparatus of claim 2 , wherein:
the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub and
based on provision of the at least some but not all home agent operations to be performed by the second home agent, the second home agent is to perform the at least some but not all home agent operations.

4. The apparatus of claim 1 , wherein the memory hub comprises a memory cache and wherein if the memory access request comprises a data read request and the memory cache includes requested data, the memory hub is to provide the requested data from the memory cache to the first processing unit.

5. The apparatus of claim 1 , comprising:
a connector between at least one processing unit of the at least two processing units and the memory hub, wherein the connector comprises one or more of: a board trace, an electrical link, an optical link, or a coaxial cable and wherein the connector comprises a parallel connection or at least one serial lane.

6. The apparatus of claim 1 , wherein:
data access times by the first processing unit and a second processing unit among the at least two processing units from a memory device via the memory hub are approximately uniform.

7. The apparatus of claim 1 , wherein:
the memory hub is to manage a coherent memory domain for access by two or more processing units among the at least two processing units from one or more memory devices.

8. The apparatus of claim 1 , comprising a server, wherein the server comprises the at least two processing units, wherein a processing unit among the at least two processing units is to execute an application or microservice that causes issuance of the memory access request to the memory hub.

9. The apparatus of claim 1 , wherein one or more of the at least two processing units comprises one or more of: an XPU, and/or an input/output interface.

10. The apparatus of claim 1 , comprising a second memory hub coupled to the at least two processing units, the second memory hub comprising a home agent, wherein:
the second memory hub is to perform a second memory access request from a processing unit among the at least two processing units, the second memory access request associated with a memory device coupled to the second memory hub.

11. The apparatus of claim 1 , wherein:
the first processing unit is to manage permission to access one or more memory regions of one or more memory devices and
the first processing unit is to delegate the management of permission to access the one or more memory regions of the one or more memory devices to the memory hub.

12. The apparatus of claim 11 , comprising a second memory hub, wherein:
the memory hub is to delegate management of permission to access the one or memory regions of the one or more memory devices to the second memory hub.

13. A method comprising:
a memory hub providing multiple processor sockets with approximately uniform access times to multiple memory devices independent from increasing a number of memory channels at a processor socket to the multiple memory devices, wherein:
the memory hub comprises a home agent to maintain cache coherency among the multiple processor sockets,
the cache coherency among the multiple processor sockets comprises access a copy of modified content of a cache line,
the multiple processor sockets comprise multiple XPUs, and
the multiple XPUs comprise multiple cores.

14. The method of claim 13 , comprising:
the multiple processor sockets accessing a memory device by providing memory access requests to the memory hub.

15. The method of claim 13 , comprising:
a processor socket among the multiple processor sockets offloading data consistency determination to the memory hub.

16. The method of claim 13 , comprising:
managing, by the memory hub, a coherent memory domain for access by the multiple processor sockets from one or more memory devices among the multiple memory devices.

17. At least one non-transitory computer-readable medium, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
cause multiple processor sockets to send memory access requests to a memory hub, wherein
the memory hub provides the multiple processor sockets with approximately uniform access times to one or more memory devices,
the memory hub comprises a home agent to maintain cache coherency among the multiple processor sockets,
the cache coherency among the multiple processor sockets comprises access a copy of modified content of a cache line,
the multiple processor sockets comprise multiple XPUs, and
the multiple XPUs comprise multiple cores.

18. The computer-readable medium of claim 17 , wherein:
the memory hub is to provide a quality of service for memory access requests from the multiple processor sockets based on priority of a requester processor socket.

19. A system comprising:
a first central processing unit (CPU) socket;
a second CPU socket;
a first memory hub comprising a first home agent; and
a second memory hub comprising a second home agent, wherein:

the first home agent of the first memory hub is to maintain cache coherency among the first and second CPU sockets,
the cache coherency among the first and second CPU sockets comprises access a copy of modified content of a cache line,
the first and second CPU sockets comprise at least one core,
the first CPU socket is to issue memory access request to the first memory hub to access a memory device connected to the first memory hub,
the first CPU socket is to issue memory access request to the second memory hub to access a second memory device connected to the second memory hub,

the second CPU socket is to issue memory access request to the first memory hub to access the memory device connected to the first memory hub, and
the second CPU socket is to issue memory access request to the second memory hub to access the second memory device connected to the second memory hub.

20. The system of claim 19 , wherein the first home agent is to perform a cache coherency operation for the first CPU socket.

21. The system of claim 19 , wherein the first CPU socket is to manage permission to access memory regions of one or more memory devices and
the first CPU socket is to delegate the management of permission to access memory regions of the one or more

Assignees

• Intel Corp

Inventors

• Galbi Duane E
• Adiletta Matthew J
• Wilkinson Hugh
• Connor Patrick

Classifications

• G06F13/1668

  Details of memory controller · CPC title

• G06F13/409

  Mechanical coupling (back panels H05K7/1438) · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title