Method for booting a heterogeneous system and presenting a symmetric core view
US-10503517-B2 · Dec 10, 2019 · US
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Fischer Stephen A patents
Fischer Stephen A is listed as an inventor on 32 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Fischer Stephen A |
| Total patents | 32 |
| First publication | Feb 19, 2015 |
| Latest publication | Dec 10, 2019 |
Notable patents
Publications ranked by popularity score, then publication date.
Protection against return oriented programming attacks
US-10049212-B2 · Aug 14, 2018 · US
Detection of return oriented programming attacks
US-9946875-B2 · Apr 17, 2018 · US
Method for booting a heterogeneous system and presenting a symmetric core view
US-2018060078-A1 · Mar 1, 2018 · US
Method and apparatus for a zero voltage processor sleep state
US-9874925-B2 · Jan 23, 2018 · US
Method and apparatus for a zero voltage processor sleep state
US-9870044-B2 · Jan 16, 2018 · US
Method and apparatus for a zero voltage processor sleep state
US-9841807-B2 · Dec 12, 2017 · US
Method And Apparatus For A Zero Voltage Processor Sleep State
US-2017269672-A9 · Sep 21, 2017 · US
Method for booting a heterogeneous system and presenting a symmetric core view
US-9727345-B2 · Aug 8, 2017 · US
Mfence and lfence micro-architectural implementation method and system
US-2017206088-A1 · Jul 20, 2017 · US
Recent patents
Latest publications not already listed above.
Detection Of Return Oriented Programming Attacks
US-2017116414-A1 · Apr 27, 2017 · US
MFENCE and LFENCE micro-architectural implementation method and system
US-9612835-B2 · Apr 4, 2017 · US
Detection of return oriented programming attacks
US-9582663-B2 · Feb 28, 2017 · US
Method And Apparatus For A Zero Voltage Processor Sleep State
US-2017017297-A1 · Jan 19, 2017 · US
Method and apparatus for a non-deterministic random bit generator (NRBG)
US-9544139-B2 · Jan 10, 2017 · US
MFENCE and LFENCE micro-architectural implementation method and system
US-9383998-B2 · Jul 5, 2016 · US
MFENCE and LFENCE micro-architectural implementation method and system
US-9342310-B2 · May 17, 2016 · US
Method and apparatus for a zero voltage processor sleep state
US-2016091958-A1 · Mar 31, 2016 · US
Detection Of Return Oriented Programming Attacks
US-2016085966-A1 · Mar 24, 2016 · US
Detection of return oriented programming attacks
US-9251348-B2 · Feb 2, 2016 · US
Protection Against Return Oriented Programming Attacks
US-2016012229-A1 · Jan 14, 2016 · US
Method and apparatus for a zero voltage processor
US-9235258-B2 · Jan 12, 2016 · US
Detection of return oriented programming attacks
US-9223979-B2 · Dec 29, 2015 · US
Method and apparatus for a zero voltage processor
US-9223390-B2 · Dec 29, 2015 · US
Method and apparatus for a zero voltage processor
US-9223389-B2 · Dec 29, 2015 · US
Protection against return oriented programming attacks
US-9177147-B2 · Nov 3, 2015 · US
Protection against return oriented programming attacks
US-9177148-B2 · Nov 3, 2015 · US
Method and apparatus for a zero voltage processor sleep state
US-9141180-B2 · Sep 22, 2015 · US
MFENCE and LFENCE micro-architectural implementation method and system
US-9098268-B2 · Aug 4, 2015 · US
Method And Apparatus For A Zero Voltage Processor Sleep State
US-2015169043-A1 · Jun 18, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 31 |
| Fischer Stephen A | 4 |
| Palanca Salvador | 3 |
| Maiyuran Subramaniam | 3 |
| Qawami Shekoufeh | 3 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| Y02D10/00 | 16 |
| G06F1/3293 | 16 |
| G06F1/3275 | 13 |
| G06F2212/305 | 13 |
| G06F1/3203 | 13 |