Method and apparatus for a zero voltage processor

Patent metadata

Field	Value
Publication number	US-9235258-B2
Application number	US-201414254413-A
Country	US
Kind code	B2
Filing date	Apr 16, 2014
Priority date	Jul 27, 2004
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

First claim

The invention claimed is:

1. A processor comprising:
a first processor core to save at least a portion of a state of the first processor core to a cache memory and to enter a first sleep state in which the first processor core is powered off;
a second processor core to save at least a portion of a state of the second processor core to the cache memory and to enter the first sleep state in which the second processor core is powered off, wherein a processor package including the first and second processor cores is to enter a package sleep state after the first and second processor cores enter the first sleep state; and
the cache memory, wherein the cache memory is to be powered when the first and second processor cores are to be powered off, and the saved state of the first processor core and the saved state of the second processor core are to be restored when the first processor core and the second processor core transition to a mode in which the first processor core and the second processor core are to be powered on, respectively.

2. The processor of claim 1 , wherein the first processor core is to save the state of the first processor core in the cache memory.

3. The processor of claim 1 , wherein the first processor core is to enter the mode in which the first processor core is to be powered off in response to execution of an instruction by the first processor core.

4. The processor of claim 3 , wherein the second processor core is to enter the mode in which the second processor core is to be powered off in response to execution of an instruction by the second processor core.

5. The processor of claim 1 , wherein the first processor core is to restore the saved state of the first processor core when reset.

6. The processor of claim 5 , wherein the second processor core is to restore the saved state of the second processor core when reset.

7. The processor of claim 1 , wherein the first processor core is to transition to the mode in which the first processor core is to be powered on in response to a signal from a power management controller.

8. The processor of claim 7 , wherein the second processor core is to transition to the mode in which the second processor core is to be powered on in response to a signal from the power management controller.

9. The processor of claim 1 , wherein the first processor core is to save and restore registers of the first processor core.

10. The processor of claim 1 , wherein the first processor core is to save and restore a debug state of the first processor core.

11. The processor of claim 1 , wherein the cache memory comprises a static random access memory.

12. The processor of claim 1 , further comprising a power management unit to control transition of the first processor core between a first operating point and a second operating point.

13. A system comprising:
a processor including at least a first core and a second core and a dedicated cache memory; and
a voltage regulator coupled to the processor to provide an operational voltage to the processor, wherein the voltage regulator is adapted to reduce the operational voltage applied to the processor to approximately zero volts during a transition to a zero voltage power management state for the processor, and the dedicated cache memory is adapted to receive first state variables associated with the first core when the first core is to enter a first sleep state and second state variables associated with the second core when the second core is to enter the first sleep state, the processor to thereafter transition into a package sleep state comprising the zero voltage power management state, wherein the dedicated cache memory is coupled to a power source of a controller coupled to the processor that remains powered while the operational voltage applied to the processor is reduced to approximately zero volts.

14. The system of claim 13 , wherein the dedicated cache memory comprises a synchronous random access memory (SRAM) internal to a package of the processor.

15. The system of claim 13 , wherein the controller comprises an input/output controller.

16. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
saving a state of a first processor core of a processor package to a cache memory of the processor package;
entering a mode in which the first processor core is powered off in a first sleep state;
saving a state of a second processor core of the processor package to the cache memory of the processor package;
entering a mode in which the second processor core is powered off in the first sleep state;
powering the cache memory of the processor package when the first processor core and the second processor core are powered off;
entering a package sleep state of the processor package after the first processor core and the second processor core enter the first sleep state;
restoring the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered on; and
restoring the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered on.

17. The non-transitory machine-readable medium of claim 16 , wherein entering the mode in which the first processor core is powered off is in response to execution of an instruction by the first processor core, and wherein entering the mode in which the second processor core is powered off is in response to execution of an instruction by the second processor core.

18. The non-transitory machine-readable medium of claim 16 , wherein restoring the saved state of the first processor core occurs when the first processor core is reset.

Assignees

• Intel Corp

Inventors

• Jahagirdar Sanjeev
• George Varghese
• Conrad John B
• Milstrey Robert
• Fischer Stephen A
• Naveh Alon
• Rotem Shai

Classifications

• G06F2212/281

  Single cache · CPC title

• G06F1/3246

  by software initiated power-off · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• Y10T307/305

  Cross-Sectional Technologies · mapped topic